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Semiconductor device and method of making the same, circuit board, and electronic instrument 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/10
  • H01L-023/58
  • H01L-029/40
  • H01L-023/48
  • H01L-021/60
출원번호 US-0117526 (1998-10-21)
우선권정보 JP0356880 (1996-12-26)
국제출원번호 PCT/JP97/04438 (1997-12-04)
§371/§102 date 19981021 (19981021)
국제공개번호 WO-9825298 (1998-06-11)
발명자 / 주소
  • Hashimoto Nobuaki,JPX
출원인 / 주소
  • Seiko Epson Corporation, JPX
대리인 / 주소
    Oliff & Berridge, PLC.
인용정보 피인용 횟수 : 61  인용 특허 : 23

초록

A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provid

대표청구항

[ What is claimed is:] [1.]1. A method of making a semiconductor device comprising:a step of providing a member on which are formed electrodes;a step of providing a first stress relieving layer on the member, the first stress relieving layer having contact holes formed therein and depressions formed

이 특허에 인용된 특허 (23)

  1. Ohara Shinji (Tokyo JPX), Alignment accuracy check pattern.
  2. Ryan Vivian W. (Nutley NJ) Schutz Ronald J. (Warren NJ), Aluminum metallization doped with iron and copper to prevent electromigration.
  3. Tran Khanh Q., Borderless vias with HSQ gap filled metal patterns having high etching resistance.
  4. Lin Chi-Fa,TWX, Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP).
  5. Nishioka Yasushiro (Tsukuba JPX) Summerfelt Scott R. (Dallas TX) Park Kyung-ho (Tsukuba JPX) Bhattacharya Pijush (Tsukuba JPX), High-dielectric-constant material electrodes comprising sidewall spacers.
  6. Cheung Robin W. (Cupertino CA), Layered low dielectric constant technology.
  7. Jain Vivek (Milpitas CA) Pramanik Dipankar (Cupertino CA), Method and structure for suppressing stress-induced defects in integrated circuit conductive lines.
  8. Yu Chen-Hua Douglas,TWX ; Jang Syun-Ming,TWX, Method for forming intermetal dielectric with SOG etchback and CMP.
  9. Yoo Chue-San,TWX ; Lee Jin-Yuan,TWX, Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations.
  10. Murooka Fumio (Atsugi JPX) Asaba Tetsuo (Atsugi JPX) Matsumoto Shigeyuki (Atsugi JPX) Ikeda Osamu (Tokyo JPX) Ichise Toshihiko (Kawasaki JPX) Sakashita Yukihiko (Isehara JPX) Inoue Shunsuke (Atsugi J, Method of making a planar wiring in an insulated groove using alkylaluminum hydride.
  11. Shu William K. (Sunnyvale CA), Method of packing an IC die in a molded plastic employing an ultra-thin die coating process.
  12. Jun Young K. (Seoul KRX), Multilayer interconnection structure for a semiconductor device.
  13. Ishikawa Hiraku,JPX, Multilevel interconnection in a semiconductor device and method for forming the same.
  14. Han Young-Kyoo (Seoul KRX), Process for formation of an isolating layer for a semiconductor device.
  15. Ueda Satoshi,JPX ; Ueda Tetsuya,JPX ; Mayumi Shuichi,JPX, Semiconductor device and a manufacturing method thereof.
  16. Hirano Naohiko (Kawasaki JPX) Doi Kazuhide (Kawasaki JPX), Semiconductor device and method of manufacturing the same.
  17. Kawagoe Tomoya (Hyogo JPX) Oishi Akihisa (Hyogo JPX) Niiro Mitsutaka (Hyogo JPX) Dosaka Katsumi (Hyogo JPX), Semiconductor device having an alignment mark.
  18. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.
  19. Nagamine Takako (Hyogo JPX) Tamura Katuhiko (Hyogo JPX) Koyama Toru (Hyogo JPX), Semiconductor device having multi-layer film structure.
  20. Sunada Takeshi,JPX, Semiconductor device, method for manufacturing the same, apparatus for manufacturing the same.
  21. Iwasaki Tadashi (Tokyo JPX), Semiconductor integrated circuit device having multi-contact wiring structure.
  22. Kudoh Hitoshi (Kyoto JPX), Semiconductor integrated circuit protectant incorporating cold cathode field emission.
  23. Pasch Nicholas F. (Pacifica CA) Patrick Roger (Santa Clara CA), Techniques for via formation and filling.

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  3. Corisis, David J.; Brooks, Jerry M.; Schwab, Matt E.; Reynolds, Tracy V., Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices.
  4. Corisis,David J.; Brooks,Jerry M.; Schwab,Matt E.; Reynolds,Tracy V., Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices.
  5. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  6. Kim, Nam Seog; Jang, Dong Hyeon; Kang, Sa Yoon; Kwon, Heung Kyu, Chip scale packages manufactured at wafer level.
  7. Akram, Salman; Wood, Alan G., Chip-scale package and carrier for use therewith.
  8. Hashimoto, Nobuaki, Electronic board and manufacturing method thereof, electro-optical device, and electronic apparatus.
  9. Hashimoto, Nobuaki, Electronic device and method of manufacturing the same.
  10. Hedler,Harry; Irsigler,Roland; Meyer,Thorsten; Wolter,Andreas, Flexible contact-connection device.
  11. Kaneda, Yutaka; Tsutsumi, Akira; Hishinuma, Hiroyuki, Flexible printed wiring boards.
  12. Mosley,Larry E.; Palanduz,Cengiz A.; Prokofiev,Victor, Input/output routing on an electronic device.
  13. Tsai, Chung-Hao; Wang, Chuei-Tang; Yu, Chen-Hua, Mechanisms for forming bump structures over wide metal pad.
  14. Ohsumi, Takashi, Method for fabricating a semiconductor apparatus including a sealing member with reduced thermal stress.
  15. Brintzinger,Axel; Trovarelli,Octavio, Method for improving the mechanical properties of BOC module arrangements.
  16. Towle,Steven; Jones,Martha; Vu,Quat T., Method for packaging a microelectronic device using on-die bond pad expansion.
  17. Corisis,David J.; Brooks,Jerry M.; Schwab,Matt E.; Reynolds,Tracy V., Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices.
  18. Corisis,David J.; Brooks,Jerry M.; Schwab,Matt E.; Reynolds,Tracy V., Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices.
  19. Pratt, Dave; Perkins, Andy, Methods of forming through substrate interconnects.
  20. Pratt, Dave; Perkins, Andy, Methods of forming through substrate interconnects.
  21. Pratt, Dave; Perkins, Andy, Methods of forming through substrate interconnects.
  22. Pratt, Dave; Perkins, Andy, Methods of forming through substrate interconnects.
  23. Vu, Quat T.; Ton, Tuy T.; Towle, Steven, Microelectronic device having signal distribution functionality on an interfacial layer thereof.
  24. Kumamoto,Nobuhisa; Samejima,Katsumi, Process of producing semiconductor chip with surface interconnection at bump.
  25. Yoshida, Shigeyoshi; Awakura, Yoshio; Ono, Hiroshi, Radiator capable of considerably suppressing a high-frequency current flowing in an electric component.
  26. Ohsumi,Takashi, Semiconductor apparatus and method for fabricating the same.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  28. Ejiri, Hirokazu, Semiconductor device and its manufacturing method.
  29. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.
  30. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.
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  34. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  35. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  36. Satake, Nobuo, Semiconductor device and method of manufacturing the same.
  37. Hashimoto, Nobuaki, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
  38. Hashimoto, Nobuaki, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
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  40. Hashimoto,Nobuaki, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
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  43. Kurosawa, Yasunori, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
  44. Kurosawa,Yasunori, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.
  45. Hashimoto, Nobuaki, Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument.
  46. Hashimoto,Nobuaki, Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument.
  47. Nagai, Akira; Ueno, Takumi; Akahoshi, Haruo; Eguchi, Syuji; Ogino, Masahiko; Satoh, Toshiya; Nishimura, Asao; Anjoh, Ichiro, Semiconductor device comprising stress relaxation layers and method for manufacturing the same.
  48. Soeno, Akitaka, Semiconductor device having protection film with recess.
  49. Asakawa, Tatsuhiko, Semiconductor device with resin layers and wirings and method for manufacturing the same.
  50. Hashimoto, Nobuaki, Semiconductor device, circuit board, and electronic instrument.
  51. Ogino,Masahiko; Ueno,Takumi; Eguchi,Shuji; Nagai,Akira; Satoh,Toshiya; Ishii,Toshiaki; Kokaku,Hiroyoshi; Segawa,Tadanori; Tsuyuno,Nobutake; Nishimura,Asao; Anjoh,Ichiro, Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Akram,Salman; Wood,Alan G., Wafer-level package and methods of fabricating.
  60. Hammedinger, Robert; Kastner, Konrad; Maier, Martin; Obesser, Michael, Weldable contact and method for the production thereof.
  61. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.
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