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An FPGA configuration circuit including a mask register that stores mask data during configuration memory read-modify-write operations. The mask data enables a multiplexing circuit to overwrite selected memory cells in a configuration memory array with new data bit values. Data bit values from all o

An FPGA configuration circuit including a mask register that stores mask data during configuration memory read-modify-write operations. The mask data enables a multiplexing circuit to overwrite selected memory cells in a configuration memory array with new data bit values. Data bit values from all other memory cells in the configuration memory array are fed back by the multiplexing circuit. In one embodiment, the new data bit values are transmitted on a bi-directional bus and stored in a shift register. The configuration memory array is arranged in frames that are addressed by a frame address register, and the contents of an addressed frame are written to a shadow register. Under the control of the mask register, the multiplexing circuit modifies the frame data bit values stored in the shadow register using the new data bit values stored in the shift register. The contents of the shadow register are then written into the addressed frame.

대표청구항 ▼

[ What is claimed is:] [1.]1. A programmable logic device including:a plurality of configurable logic blocks connected by configurable interconnect resources;a configuration memory array including a plurality of configuration memory cells having output terminals coupled to the configurable logic blo

[ What is claimed is:] [1.]1. A programmable logic device including:a plurality of configurable logic blocks connected by configurable interconnect resources;a configuration memory array including a plurality of configuration memory cells having output terminals coupled to the configurable logic blocks and the configurable interconnect resources such that portions of the configurable logic blocks and the configurable interconnect resources are controlled by configuration data stored in a corresponding configuration memory cell, the plurality of configuration memory cells including a first configuration memory cell;a first register including a first flip-flop for storing a first data bit value read from the first configuration memory cell;a second register including a second flip-flop for storing a second data bit value;a third register including a third flip-flop for storing a mask data bit value; anda multiplexing circuit connected between the first register and the second register, the multiplexing circuit being controlled by the third register such that when the mask data bit value is a first logic level, the second bit value is written into the first flip-flop, and when the mask data bit value is a second logic level, the first flip-flop retains the first data bit value.