초록 ▼

An electronic test system used for scan testing of a device under test (DUT) is disclosed that includes a standard Automatic Test Equipment (ATE) tester and an additional test vector source apparatus called a Scanbox. The Scanbox enhances the scan pattern vector depth of any ATE system without requi

An electronic test system used for scan testing of a device under test (DUT) is disclosed that includes a standard Automatic Test Equipment (ATE) tester and an additional test vector source apparatus called a Scanbox. The Scanbox enhances the scan pattern vector depth of any ATE system without requiring significant modifications to either its software or hardware. The Scanbox consists of a memory, an address counter, compare logic, control logic, and interface circuits. The scan vector data for the test data in (TDI) and expected test data out (ETDO) signals are stored within the Scanbox. These TDI signals are sent to the DUT during the test mode of operation while the tester provides the DUT with the test clock (TCLK), test mode select (TMS), and RESET signals. The tester further provides the Scanbox with BOXCLOCK and BOXRESET signals and the Scanbox provides the tester with a BOXERROR signal that is triggered high when the scan pattern vector data from the DUT does not match the corresponding ETDO signal. The tester is able to provide these clocking signals despite not necessarily having sufficient memory to perform the scan test with use of a repeat function within the tester. This allows the regular ATE system software and hardware to control the Scanbox without any significant modifications. Typical high-speed testers have very limited scan pattern vector depth. Hence, the addition of the Scanbox can enhance the capability of these testers, so that long scan test patterns can be performed. This eliminates the need for a second slow-speed tester being used exclusively for scan testing.

대표청구항 ▼

[ What is claimed is:] [1.]1. A test vector source apparatus that is capable of scan testing a device under test (DUT) when running within an electronic test system comprising the test vector source apparatus, the DUT, and a test apparatus, the test vector source apparatus comprising:a memory storag

[ What is claimed is:] [1.]1. A test vector source apparatus that is capable of scan testing a device under test (DUT) when running within an electronic test system comprising the test vector source apparatus, the DUT, and a test apparatus, the test vector source apparatus comprising:a memory storage device that stores a plurality of test data sets sufficient for scan testing of the DUT, each test data set comprising a test data in (TDI) signal and an expected test data out (ETDO) signal, the memory storage device selectively outputting the TDI signals to the DUT and being input with a clock signal from the test apparatus via a first coupling means; anda decision device that generates an error decision signal with use of a plurality of test data out (TDO) signals input from the DUT and the ETDO signals input from the memory storage device.