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Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/476.3
출원번호 US-0459167 (1999-12-10)
발명자 / 주소
  • Rathore Hazara S.
  • Dalal Hormazdyar M.
  • McLaughlin Paul S.
  • Nguyen Du B.
  • Smith Richard G.
  • Swinton Alexander J.
  • Wachnik Richard A.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson, LLCTomaszewski
인용정보 피인용 횟수 : 22  인용 특허 : 33

초록

A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than

대표청구항

[ Thus, having described the invention, what is claimed is:] [1.]1. A method for forming multilevel interconnections of copper lines isolated from one another by dielectric insulation for making contacts to electrical features in a substrate, the method comprising the steps of:(a) preparing a substr

이 특허에 인용된 특허 (33)

  1. Stone Glen A. ; Howard Stanley M., Boron-copper-magnesium-tin alloy and method for making same.
  2. Watts David ; Bajaj Rajeev ; Das Sanjit ; Farkas Janos ; Dang Chelsea ; Freeman Melissa ; Saravia Jaime A. ; Gomez Jason ; Cook Lance B., Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture.
  3. Shapiro Stanley (New Haven CT) Shapiro Eugene (Hamden CT) Mravic Brian (North Haven CT) Watson W. Gary (Cheshire CT), Copper base alloys with high strength and high electrical conductivity.
  4. Woodford David A. (Schenectady NY) Bricknell Rodger H. (Schenectady NY), Copper-base alloys containing strengthening and ductilizing amounts of hafnium and zirconium and method.
  5. Bernhardt Anthony F. (Berkeley CA) Contolini Robert J. (Pleasanton CA), Electrochemical planarization.
  6. Thomas Michael E. (Cupertino CA), High temperature interconnect system for an integrated circuit.
  7. Colgan Evan G. (Suffern NY) Rodbell Kenneth P. (Poughguag NY) Totta Paul A. (Poughkeepsie NY) White James F. (Newburgh NY), Interconnect structure using a Al2Cu for an integrated circuit chip.
  8. Howard James Kent (Fishkill NY) Ho Paul Siu-Chung (Mahopac NY), Intermetallic compound layer in thin films for improved electromigration resistance.
  9. Eschbach Rudolph J. B. (Amenia NY), Manufacturing system for low temperature chemical vapor deposition of high purity metals.
  10. Howard James K. (Fishkill NY) Ho Paul S. (Mahopac NY), Method for forming intermetallic layers in thin films for improved electromigration resistance.
  11. Dalal, Hormazdyar M.; Lowney, John J., Method for making low barrier Schottky devices of the electron beam evaporation of reactive metals.
  12. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  13. Nguyen Du B. (Danbury CT) Rathore Hazara S. (Stormville NY), Method for producing interlevel stud vias.
  14. Miracky Robert (Cedar Park TX) Yater Joan E. (Austin TX) Mackay Colin A. (Austin TX), Method of depositing conductive lines on a dielectric.
  15. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  16. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
  17. Holmes Robert E. (Portland OR) Zimmerman Robert R. (Beaverton OR), Method of making a metalized substrate having a thin film barrier layer.
  18. Chang Kenneth (Hopewell Junction NY) Czornyj George (Poughkeepsie NY) Farooq Mukta S. (Hopewell Junction NY) Kumar Ananda H. (Hopewell Junction NY) Pitler Marvin S. (late of Poughkeepsie NY by Peter , Method of making a multilayer thin film structure.
  19. Krishnan Ajay (Austin TX) Kumar Nalin (Austin TX), Multilevel metallization process for electronic components.
  20. Jain Ajay, Process for forming a semiconductor device.
  21. Gelatos Avgerinos V. (Austin TX) Fiordalice Robert W. (Austin TX), Process for forming copper interconnect structure.
  22. Norman John A. T. (Encinitas CA) Hochberg Arthur K. (Solana Beach CA) Roberts David A. (Carlsbad CA), Process for improved quality of CVD copper films.
  23. Dyer Paul N. (Allentown PA) Fine Stephen M. (Emmaus PA) Norman John A. T. (Encinitas CA), Process for selectively depositing copper aluminum alloy onto a substrate.
  24. Sachdev Krishna G. (Hopewell Junction NY) Kellner Benedikt M. J. (Wappingers Falls NY) McGuire Kathleen M. (Wallkill NY) Sorce Peter J. (Poughkeepsie NY), Process for thin film interconnect.
  25. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  26. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  27. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  28. Matsuno Tadashi,JPX, Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first.
  29. Akutsu Hidetoshi (Kitamoto JPX) Iwamura Takuro (Omiya JPX) Kobayashi Masao (Omiya JPX), Semiconductor device having copper alloy leads.
  30. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.
  31. Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
  32. Dalal Hormazdyar M. (Milton NY) Hutchings Kevin J. (Middletown NY) Rathore Hazara S. (Stormville NY), Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines.
  33. Norman John A. T. (Encinitas CA), Volatile precursors for copper CVD.

이 특허를 인용한 특허 (22)

  1. Hu, Yonjun Jeff, Agglomeration control using early transition metal alloys.
  2. Hu,Yonjun Jeff, Agglomeration control using early transition metal alloys.
  3. Hu,Yonjun Jeff, Agglomeration control using early transition metal alloys.
  4. Shekhar Pramanick ; John A. Iacoponi, Alloy barrier layers for semiconductors.
  5. Lin,Shih Ho; Chen,Chung Chang; Chen,Kei Wei; Chang,Shih Tzung; Chen,Chao Lung; Shih,Po Jen; Lin,Yu Ku; Wang,Ying Lang, Electropolishing method for removing particles from wafer surface.
  6. Lindgren, Peter J.; Sprogis, Edmund J.; Stamper, Anthony K., IC chip and design structure with through wafer vias dishing correction.
  7. Kim,Jung Joo, Method for fabricating semiconductor device.
  8. Kim,Jung Joo, Method of fabricating semiconductor device.
  9. Lee,Hsien Ming; Su,Hung Wen, Method of forming a robust copper interconnect by dilute metal doping.
  10. Zheng, Wen Yue; Mao, Gang; Cui, Jian Fei, Method to eliminate Cu dislocation for reliability and yield.
  11. Fu, Xinyu; Sundarrajan, Arvind, Methods for reducing damage to substrate layers in deposition processes.
  12. Kim,Jung Joo, Methods of fabricating via hole and trench.
  13. Christy Mei-Chu Woo ; Pin-Chin Connie Wang ; Amit Marathe ; Diana M. Schonauer, Selective copper alloy deposition.
  14. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.
  15. Saito,Tatsuyuki; Ohashi,Naohumi; Imai,Toshinori; Noguchi,Junji; Tamaru,Tsuyoshi, Semiconductor integrated circuit device.
  16. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.
  17. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.
  18. Agarwala, Birendra N.; Nguyen, Du B.; Rathore, Hazara S., Structure and method for eliminating time dependent dielectric breakdown failure of low-k material.
  19. Chang, Chung-Liang; Shue, Shaulin, Technique to enhance the yield of copper interconnections.
  20. Lindgren, Peter J.; Sprogis, Edmund J.; Stamper, Anthony K., Through wafer vias with dishing correction methods.
  21. Lindgren, Peter J.; Sprogis, Edmund J.; Stamper, Anthony K., Through wafer vias with dishing correction methods.
  22. Marathe, Amit P.; Erb, Darrell M., Use of an alloying element to form a stable oxide layer on the surface of metal features.
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