초록 ▼

An inverting hysteretic transistor switch having an input terminal, an output terminal and a ground terminal includes, in some embodiments, a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal conne

An inverting hysteretic transistor switch having an input terminal, an output terminal and a ground terminal includes, in some embodiments, a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hyteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

대표청구항 ▼

[ What is claimed is:] [1.]1. An inverting hysteretic transistor switch having only three terminals, said three terminals being an input terminal, an output terminal and a ground terminal, said inverting hysteretic transistor switch comprising:a. a first field effect transistor (FET) having a drain

[ What is claimed is:] [1.]1. An inverting hysteretic transistor switch having only three terminals, said three terminals being an input terminal, an output terminal and a ground terminal, said inverting hysteretic transistor switch comprising:a. a first field effect transistor (FET) having a drain terminal, a source terminal and a gate terminal, the source terminal of said first FET being connected to the ground terminal;b. a second field effect transistor (FET) having a drain terminal, a source terminal and a gate terminal, the source terminal of said second FET being connected to the ground terminal and the gate terminal of said second FET being connected to the drain terminal of said first FET;c. a third field effect transistor (FET) having a drain terminal, a source terminal and a gate terminal, the source terminal of said third FET being connected to the ground terminal, the drain terminal of said third FET being connected to the output terminal and the gate terminal of said third FET being connected to the gate terminal of said first FET;d. a first resistor having a first terminal and a second terminal, the first terminal of said first resistor being connected to the input terminal and the second terminal of said first resistor being connected to the drain terminal of said first FET;e. a second resistor having a first terminal and a second terminal, the first terminal of said second resistor being connected to the input terminal and the second terminal of said second resistor being connected to the gate terminal of said first FET; andf. a third resistor having a first terminal and a second terminal, the first terminal of said third resistor is connected to the gate terminal of said first FET and the second terminal of said third resistor is connected to the drain terminal of said second FET.