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System architecture for and method of processing packets and/or cells in a common switch 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-012/28
출원번호 US-0001040 (1997-12-30)
발명자 / 주소
  • Opalka Zbigniew
  • Aggarwal Vijay
  • Kong Thomas
  • Firth Christopher
  • Costantino Carl
출원인 / 주소
  • Nexabit Networks, LLC
대리인 / 주소
    Rines and Rines
인용정보 피인용 횟수 : 298  인용 특허 : 3

초록

A novel networking architecture and technique for transmitting both cells and packets or frames across a common switch fabric, effected, at least in part, by utilizing a common set of algorithms for the forwarding engine (the ingress side) and a common set of algorithms for the QoS management (the e

대표청구항

[ What is claimed is:] [5.]5. A method of processing packets of information from a forwarding switch and queue managing the forwarding, that comprises, as each packet is read from the switch, putting the same into one of a plurality of queues after it is verified that available physical space exists

이 특허에 인용된 특허 (3)

  1. Munter Ernst A. (Kanata CAX), Common memory switch for routing data signals comprising ATM and STM cells.
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  3. Wright Tim ; Marconi Peter ; Conlin Richard ; Opalka Zbigniew, System architecture for and method of dual path data processing and management of packets and/or cells and the like.

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