An improvement for obtaining synchronization to a chip-sequence signal. The chip-sequence signal has a plurality of chips, and is embedded in a spread-spectrum signal. A shift register shifts or cycles a replica or delayed replica of the chip-sequence signal. The shift register has a plurality of ta
An improvement for obtaining synchronization to a chip-sequence signal. The chip-sequence signal has a plurality of chips, and is embedded in a spread-spectrum signal. A shift register shifts or cycles a replica or delayed replica of the chip-sequence signal. The shift register has a plurality of taps, which correspond to the plurality of chips. A plurality of comparators compares the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in the shift register. From the comparison, the plurality of comparators generates, for each tap of the shift register, a plurality of compared values at each comparator of the plurality of comparators. A plurality of counters up and down counts, from each comparator, a respective plurality of compared values. The respective plurality of compared values appears at an output of a respective comparator of the plurality of comparators. The plurality of counters thereby generates a plurality of totals, respectively. A selector device selects a value from the plurality of totals. The selected value may be, by way of example, a largest value, a maximum likely value. The invention can be extended to one or more samples per chip, and each sample may have one bit for hard decision, or more bits for soft decision.
대표청구항▼
[ I claim:] [1.]1. An improvement for acquiring synchronization to a chip-sequence signal having, a plurality of chips, embedded in a spread-spectrum signal, comprising:a shift register for storing a replica or delayed replica of the chip-sequence signal, with said shift register having a plurality
[ I claim:] [1.]1. An improvement for acquiring synchronization to a chip-sequence signal having, a plurality of chips, embedded in a spread-spectrum signal, comprising:a shift register for storing a replica or delayed replica of the chip-sequence signal, with said shift register having a plurality of taps corresponding to the plurality of chips, respectively;a plurality of comparators, connected to the plurality of taps, respectively, for comparing the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values;a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters; andselecting means, coupled to said plurality of counters, for selecting a value from the plurality of totals.
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이 특허에 인용된 특허 (3)
Sands Jeffrey J. ; Turner Michael D., Apparatus and method for detecting frame synchronization pattern/word in bit-stuffed digital data frame.
Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
Heidari,Ghobad; Chang,Kuor Hsin; Master,Paul L.; Hogenauer,Eugene B.; Scheuermann,Walter James, Method and system for implementing a system acquisition function for use with a communication device.
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