초록 ▼

The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a re

The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a reconfiguration sequence that, in turn, causes the signal received from the output terminal to be ignored. Therefore, the method of the invention is reliably stable and does not undesirably repeat, oscillate, or fail. The FPGA may initiate its own reconfiguration upon detecting that a new configuration bitstream has been selected for downloading from an external device such as a PROM. The FPGA may detect the actuation of a binary or rotary switch. Alternatively, the FPGA may detect when a CMOS latch or register points to a new configuration address in the PROM. In one embodiment, an external memory device stores FPGA state information from one reconfiguration cycle to the next.

대표청구항 ▼

[ What is claimed is:] [1.]1. A self-reprogrammable system, comprising:an input terminal;an output terminal in electrical communication with the input terminal;output control means, responsive to a reconfiguration request signal, for driving a signal on the output terminal into a first state and cau

[ What is claimed is:] [1.]1. A self-reprogrammable system, comprising:an input terminal;an output terminal in electrical communication with the input terminal;output control means, responsive to a reconfiguration request signal, for driving a signal on the output terminal into a first state and causing the system to enter a reconfiguration mode in response to detection of the first state on the input terminal;a monitoring circuit for detecting a monitored characteristic of an external signal, the monitoring circuit including means for generating the reconfiguration request signal in response to detection of a change in the monitored characteristic of the external signal.