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Method of forming shallow trench isolation structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
출원번호 US-0395110 (1999-09-14)
우선권정보 TW8113097 (1999-07-31)
발명자 / 주소
  • Yen Ching-Lang,TWX
  • Lin Chingfu,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Co., Ltd., TWX
대리인 / 주소
    Huang
인용정보 피인용 횟수 : 70  인용 특허 : 8

초록

A method of forming a shallow trench isolation structure is described. A mask layer and a photoresist layer with an opening are formed on a substrate in sequence. The photoresist layer serves as an etching mask, and then a portion of the mask layer and a portion of the substrate are etched to form a

대표청구항

[ What is claimed is:] [1.]1. A method of forming a shallow trench isolation structure, comprising the steps of:providing a substrate;forming a pad oxide layer on the substrate;forming a silicon nitride layer on the pad oxide layer;forming a photoresist layer with an opening on the silicon nitride l

이 특허에 인용된 특허 (8)

  1. Chen Chao-Cheng,TWX ; Tsai Chia-Shiung,TWX, Achievement of top rounding in shallow trench etch.
  2. Tan Poh Suan,SGX ; Chan Lap ; Zhong Qinghua,SGX ; Gang Qian,SGX, Method for making improved shallow trench isolation for semiconductor integrated circuits.
  3. Kuo Chien-Li,TWX, Method for manufacturing shallow trench isolation.
  4. Kuo Chien-Li,TWX, Method for manufacturing shallow trench isolation structure.
  5. Oh Yong-chul,KRX ; Park Young-Woo,KRX, Method of forming an isolation trench in a semiconductor device including annealing at an increased temperature.
  6. Li Jian Xun,SGX ; Zhong Qing Hua,SGX ; Zhou Mei Sheng,SGX, Method to form shallow trench isolation structures.
  7. Kelley Patrick J. ; Singh Ranbir ; Fritzinger Larry B. ; Lee Cynthia C. ; Molloy John Simon, Shallow trench isolation method providing rounded top trench corners.
  8. Hong Soo-jin,KRX ; Shin Yu-gyun,KRX ; Lee Han-sin,KRX ; Choe Hyun-cheol,KRX, Trench isolation method for semiconductor device.

이 특허를 인용한 특허 (70)

  1. Bryant, Andres; Cottrell, Peter E.; Ellis-Monaghan, John J.; Gauthier, Jr., Robert J.; Nowak, Edward J.; Rankin, Jed H.; Assaderaghi, Fariborz, Body contact MOSFET.
  2. Bryant, Andres; Cottrell, Peter E.; Ellis-Monaghan, John J.; Gauthier, Jr., Robert J.; Nowak, Edward J.; Rankin, Jed H.; Assaderaghi, Fariborz, Body contact MOSFET.
  3. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  5. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  6. Yamashita, Takeshi; Yamaguchi, Takao; Niko, Hideo, Dry etching method, fabrication method for semiconductor device, and dry etching apparatus.
  7. Yamashita,Takeshi; Yamaguchi,Takao; Niko,Hideo, Dry etching method, fabrication method for semiconductor device, and dry etching apparatus.
  8. Yamashita,Takeshi; Yamaguchi,Takao; Niko,Hideo, Dry etching method, fabrication method for semiconductor device, and dry etching apparatus.
  9. Yamashita,Takeshi; Yamaguchi,Takao; Niko,Hideo, Dry etching method, fabrication method for semiconductor device, and dry etching apparatus.
  10. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Lin, Yu-Ying; Ku, Kuan Hsuan; Hu, I-Cheng; Liu, Chueh-Yang; Lu, Shui-Yen; Lin, Yu Shu; Yang, Chun Yao; Wang, Yu-Ren; Yang, Neng-Hui, Field-effect transistor.
  21. Freywald, Karlheinz, Filling of insulation trenches using CMOS standard processes for creating dielectrically insulated areas on a SOI disk.
  22. DeLoach,Juanita; Smith,Brian A., In situ hardmask pullback using an in situ plasma resist trim process.
  23. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  24. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  25. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  26. David L. Dickerson ; Richard H. Lane ; Charles H. Dennison ; Kunal R. Parekh ; Mark Fischer ; John K. Zahurak, Isolation region forming methods.
  27. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  28. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  29. Bartlau, Peter H.; Cantell, Marc W.; Lasky, Jerome B.; Weil, James D., Method for limiting divot formation in post shallow trench isolation processes.
  30. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  31. Palanivel Balasubramanian SG; Yelehanka Ramachandramurthy Pradeep SG; Chivkula Subrahmanyam SG; Narayanan Balasubramanian SG, Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner.
  32. Chen, Yi-Nan; Hao, Chung Peng; Lee, Chung-Yuan, Method of fabricating shallow trench isolation.
  33. Shim, Cheon Man, Method of forming a device isolation film of a semiconductor device.
  34. Chiu, Yih Song; Huang, Jao Sheng; Tsai, Wen Ting; Leu, Chen Hsiang, Method of forming an STI feature to avoid electrical charge leakage.
  35. Sawamura, Kenji, Method of forming isolation film.
  36. Lim, Hyun-Ju, Method of manufacturing semiconductor device.
  37. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  38. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  39. Ramkumar, Krishnaswamy, Methods of forming semiconductor structures, and articles and devices formed thereby.
  40. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  41. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  42. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  43. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  44. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  47. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  48. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  49. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  50. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  51. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  52. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  53. Chen,Chien Hao; Chang,Vincent S.; Yang,Ji Yi; Chen,Chia Lin; Lee,Tze Liang, Selective nitride liner formation for shallow trench isolation.
  54. Chen,Chien Hao; Chang,Vincent S.; Yang,Ji Yi; Chen,Chia Lin; Lee,Tze Liang, Selective nitride liner formation for shallow trench isolation.
  55. Shibata,Akihide; Iwata,Hiroshi; Kakimoto,Seizo, Semiconductor device having device isolation region and portable electronic device.
  56. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  57. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  58. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  59. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  60. Borthakur, Swarnal; Stocks, Richard L., Semiconductor processing methods.
  61. Borthakur, Swarnal; Stocks, Richard L., Semiconductor processing methods.
  62. Angela Hui, Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding.
  63. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  64. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  65. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  66. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  67. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  68. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  69. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  70. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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