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Dual damascene method employing spin-on polymer (SOP) etch stop layer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0387440 (1999-09-01)
발명자 / 주소
  • Jang Syun-Ming,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 33  인용 특허 : 8

초록

A method for forming upon a substrate employed within a microelectronics fabrication a dual damascene stacked conductor interconnection layer. There is provided a substrate employed within a microelectronics fabrication wherein a series of conductor regions comprising a microelectronics conductor la

대표청구항

[ What is claimed is:] [1.]1. A method for forming upon a substrate employed within a microelectronics fabrication a dual damascene structure comprising:providing a substrate having contact regions formed thereon;forming over the substrate a first dielectric layer;forming upon the first dielectric l

이 특허에 인용된 특허 (8)

  1. Greco Stephen E. (LaGrangeville NY) Srikrishnan Kris V. (Wappingers Falls NY), Chip interconnection having a breathable etch stop layer.
  2. Yu Chen-Hua Douglas,TWX ; Jang Syun Ming,TWX, Dual damascene patterned conductor layer formation method without etch stop layer.
  3. You Lu ; Cheung Robin W. ; Chan Simon S. ; Huang Richard J., Low RC interconnection.
  4. Fiordalice Robert W. (Austin TX) Maniar Papu D. (Austin TX) Klein Jeffrey L. (Austin TX), Method for forming inlaid interconnects in a semiconductor device.
  5. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  6. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  7. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  8. Lee Eddie ; Grimley JoAnn, Surface conditioning insulating layer for fine line conductive pattern.

이 특허를 인용한 특허 (33)

  1. Rakesh Kumar SG; Leong Tee Koh MY; Pang Dow Foo SG, Bi-layer resist process for dual damascene.
  2. Prakash, Shiva; Troung, Nugent, Device patterning using irradiation.
  3. Park, Geon-Ook, Fabrication method of semiconductor device.
  4. Ramkumar Subramanian ; Minh Van Ngo ; Suzette K. Pangrle ; Kashmir Sahota ; Christopher F. Lyons, Method for creating partially UV transparent anti-reflective coating for semiconductors.
  5. Ramkumar Subramanian ; Minh Van Ngo ; Kashmir Sahota ; Yongzhong Hu ; Hiroyuki Kinoshita ; Fei Wang ; Wenge Yang, Method for eliminating anti-reflective coating in semiconductors.
  6. Pyo, Sung Gyu, Method for forming metal line in a semiconductor device.
  7. Chung-Yeh Lee TW; Pei-Ren Jeng TW; Henry Chung TW, Method for forming self-aligned mask read only memory by dual damascene trenches.
  8. Liu, Yu-Lun; Liu, Chia-Chu; Chen, Kuei-Shun; Wang, Chung-Ming; Lin, Chie-Chieh, Method for improving resist pattern peeling.
  9. Liu, Yu-Lun; Liu, Chia-Chu; Chen, Kuei-Shun; Wang, Chung-Ming; Lin, Chie-Chieh, Method for making a lithography mask.
  10. Hwang, Sang-Il; Lim, Hyun Ju, Method of forming dual damascene pattern.
  11. Hongning Yang ; Tue Nguyen, Method to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon using a silicon carbide adhesion promoter layer.
  12. Prakash,Shiva, Organic electronic device.
  13. Annapragada, Rao V.; Morey, Ian J.; Ho, Chok W., Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications.
  14. Prakash, Shiva, Process for removing an organic layer during fabrication of an organic electronic device.
  15. Prakash,Shiva; Li,Feng; Lopez Gutierrez,Linnette Amarilys, Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process.
  16. Bohr, Mark T.; Ghani, Tahir; Rahhai-Orabi, Nadia M.; Joshi, Subhash M.; Steigerwald, Joseph M.; Klaus, Jason W.; Hwang, Jack; Mackiewicz, Ryan, Self-aligned contacts.
  17. Bohr, Mark T.; Ghani, Tahir; Rahhal-Orabi, Nadia M.; Joshi, Subhash M.; Steigerwald, Joseph M.; Klaus, Jason W.; Hwang, Jack; Mackiewicz, Ryan, Self-aligned contacts.
  18. Bohr, Mark T.; Ghani, Tahir; Rahhal-Orabi, Nadia M.; Joshi, Subhash M.; Steigerwald, Joseph M.; Klaus, Jason W.; Hwang, Jack; Mackiewicz, Ryan, Self-aligned contacts.
  19. Bohr, Mark T.; Ghani, Tahir; Rahhal-Orabi, Nadia M.; Joshi, Subhash M.; Steigerwald, Joseph M.; Klaus, Jason W.; Hwang, Jack; Mackiewicz, Ryan, Self-aligned contacts.
  20. Bohr, Mark T.; Ghani, Tahir; Rahhal-Orabi, Nadia M.; Joshi, Subhash M.; Steigerwald, Joseph M.; Klaus, Jason W.; Hwang, Jack; Mackiewicz, Ryan, Self-aligned contacts.
  21. Brase, Gabriela, Self-aligned dual damascene etch using a polymer.
  22. Koike, Junichi, Semiconductor device, its manufacturing method, and sputtering target material for use in the method.
  23. Sung, Su-Jen; Su, Yi-Nien, Semiconductor devices and methods of manufacture thereof.
  24. Ramkumar Subramanian ; Wenge Yang ; Marina V. Plat ; Lewis Shen, Semiconductor manufacturing method using a dielectric photomask.
  25. Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods.
  26. Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods utilizing low concentrations of reactive etching components.
  27. Torek, Kevin J.; Bedge, Satish, Semiconductor processing methods utilizing low concentrations of reactive etching components.
  28. Liu, Wei; He, Jim Zhongyi; Ahn, Sang H.; Shen, Meihua; M'Saad, Hichem; Yeh, Wendy H.; Bencher, Christopher D., Techniques for the use of amorphous carbon (APF) for various etch and litho integration schemes.
  29. Lin, Yung-Chi; Chen, Yi-Hsiu; Yang, Ku-Feng; Chiou, Wen-Chih, Through-substrate via formation with improved topography control.
  30. Lin, Yung-Chi; Chen, Yi-Hsiu; Yang, Ku-Feng; Chiou, Wen-Chih, Through-substrate via formation with improved topography control.
  31. Townsend, III, Paul H.; Mills, Lynne K.; Waeterloos, Joost J. M.; Strittmatter, Richard J., Tri-layer masking architecture for patterning dual damascene interconnects.
  32. Guha, Subhendu; Banerjee, Arindam; Beernink, Kevin; Johnson, Todd; Pietka, Ginger; DeMaggio, Gregory; Liu, Shengzhong (Frank); Yang, Jeffrey, Ultra lightweight photovoltaic device and method for its manufacture.
  33. Ho, Chok W., Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics.
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