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Package stack via bottom leaded plastic (BLP) packaging 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0641623 (2000-08-18)
발명자 / 주소
  • Tandy Patrick W.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 81  인용 특허 : 30

초록

A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom packag

대표청구항

[ What is claimed is:] [1.]1. A packaged semiconductor device assembly having leads on a bottom thereof comprising:a semiconductor die;a lead frame including at least one lead with upper surface, lower surface, and side surfaces, said at least one lead comprising:an inner lead connected to said semi

이 특허에 인용된 특허 (30)

  1. Variot Patrick (San Jose CA), Apparatus for encapsulating an integrated circuit package.
  2. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  3. Kierse Oliver J. (County Clare IEX), EMF shielding of an integrated circuit package.
  4. Russell Ernest J. (Richmond TX) Baudouin Daniel A. (Missouri City TX) Le Duy-Loan T. (Missouri City TX) Wallace James (Sugar Land TX), High density semiconductor package.
  5. Whitehead Graham K. (Ipswich GB2) Taylor Kenneth (East Barnet GB2), Integrated circuit chip carrier.
  6. Heinen Katherine G. (Dallas TX), Integrated circuit device and method to prevent cracking during surface mount.
  7. Chun Heung Sup (Seoul KRX), Integrated double-chip semiconductor package and method for fabricating same.
  8. Hernandez Jorge M. (Mesa AZ) Hyslop Michael S. (Chandler AZ), Internally decoupled integrated circuit package.
  9. Song Chi J. (Daejon KRX), Lead frame and semiconductor package with such lead frame.
  10. Casto James J. (Austin TX), Leadless semiconductor device and method for making the same.
  11. Variot Patrick (San Jose CA), Method for encapsulating an integrated circuit package.
  12. King Jerrold L. (Boise ID) Moden Walter L. (Boise ID) Huang Chender (Boise ID), Method for producing high speed integrated circuits.
  13. Tomita Yoshihiro (Itami JPX) Ueda Naoto (Itami JPX) Nishinaka Yoshirou (Itami JPX) Abe Shunichi (Itami JPX) Ichiyama Hideyuki (Itami JPX), Method of making a lead on chip (LOC) semiconductor device.
  14. Chia Chok J. (Santa Clara CA), Method of molding a pin grid array package.
  15. Chun Heung S. (Seoul KRX), Multi-chip semiconductor package.
  16. Loh Wah K. (Richardson TX), Packaged integrated circuit with encapsulated electronic devices.
  17. Hasegawa Miki (Kyoto JPX), Packaging device and its manufacturing method.
  18. Arikawa Tadashi (Toyama JPX) Tsuchiya Mitsuru (Toyama JPX) Ichida Akira (Toyama JPX) Igarashi Tadashi (Toyama JPX), Plastic-packaged semiconductor device having a heat sink matched with a plastic package.
  19. Hasegawa Miki (Kyoto JPX), Resin-packaged electronic component.
  20. Murakami Gen (Machida JPX) Tsubosaki Kunihiro (Hino JPX) Ichitani Masahiro (Kodaira JPX) Nishi Kunihiko (Kokubunji JPX) Anjoh Ichiro (Koganei JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Shimoinay, Semiconductor device.
  21. Kasai Junichi (Kawasaki JPX) Tsuji Kazuto (Kawasaki JPX) Taniguchi Norio (Kawasaki JPX) Mashiko Takashi (Kawasaki JPX) Sakuma Masao (Kawasaki JPX) Saigo Yukio (Satsuma JPX) Yoneda Yoshiyuki (Kawasaki, Semiconductor device and carrier for carrying semiconductor device.
  22. Hara Akitoshi (Suwa JPX), Semiconductor device and its manufacturing method.
  23. Sato Mitsutaka (Kawasaki JPX) Kasai Junichi (Kawasaki JPX), Semiconductor device and method of producing the same.
  24. Yamashita Chikara,JPX, Semiconductor device having a perforated base film sheet.
  25. Waki Masaki (Sagamihara JPX) Kasai Junichi (Kawasaki JPX) Aoki Tsuyoshi (Sagamihara JPX) Honda Toshiyuki (Kawasaki JPX) Sato Hirotaka (Kawasaki JPX), Semiconductor device having a plurality of chips.
  26. Hatakeyama Atsushi (Kawasaki JPX) Baba Fumio (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Sato Mitsutaka (Kawasaki JPX), Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package.
  27. Honda Tosiyuki (Kawasaki JPX) Haranosono Takao (Satsuma JPX), Semiconductor device having a plurality of semiconductor chips.
  28. Fujisawa Tetsuya,JPX ; Sato Mitsutaka,JPX ; Kasai Junichi,JPX ; Mizukoshi Masataka,JPX ; Otokita Kousuke,JPX ; Yoshimura Hiroshi,JPX ; Hayashida Katsuhiro,JPX ; Takashima Akira,JPX ; Ishiguri Masahik, Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plasti.
  29. Kawahara Toshimi (Kawasaki JPX) Nakaseko Shinya (Kawasaki JPX) Osawa Mitsunada (Kawasaki JPX) Taniguchi Shinichirou (Kagoshima JPX) Osumi Mayumi (Kawasaki JPX) Ishiguro Hiroyuki (Kawasaki JPX) Katoh , Semiconductor device having resin gate hole through substrate for resin encapsulation.
  30. Park Jong Y. (Bucheon KRX) Choi Jong K. (Incheon KRX), Surface mount semiconductor package.

이 특허를 인용한 특허 (81)

  1. Goodwin,Paul; Wehrly, Jr.,James Douglas, Active cooling methods and apparatus for modules.
  2. Goodwin,Paul, Buffered thin module system and method.
  3. Roeters,Glen E; Ross,Andrew C, CSP chip stack with flex circuit.
  4. Szewerenko, Leland; Partridge, Julian; Orris, Ron, Circuit module having force resistant construction.
  5. Szewerenko,Leland; Partridge,Julian; Orris,Ron, Circuit module having force resistant construction.
  6. Szewerenko, Leland; Partridge, Julian; Lieberman, Wayne; Goodwin, Paul, Circuit module turbulence enhancement systems and methods.
  7. Wehrly, Jr.,James Douglas; Wilder,James; Wolfe,Mark; Goodwin,Paul, Circuit module with thermal casing systems.
  8. Cady, James W.; Wehrly, Jr., James Douglas; Goodwin, Paul, Compact module system and method.
  9. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  10. Cady, James W.; Goodwin, Paul, Die module system.
  11. Cady,James W.; Goodwin,Paul, Die module system.
  12. Thomas, John; Rapport, Russell; Washburn, Robert, Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area.
  13. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
  14. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Flex-based circuit module.
  15. Wehrly, Jr., James Douglas; Wilder, James; Goodwin, Paul; Wolfe, Mark, Heat sink for a high capacity thin module system.
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  27. Goodwin,Paul, Inverted CSP stacking system and method.
  28. Seng,Eric Tan Swee; Chye,Lim Thiam, Invertible microfeature device packages.
  29. Seng,Eric Tan Swee; Lim,Thiam Chye, Invertible microfeature device packages.
  30. Cady,James W.; Partridge,Julian; Wehrly, Jr.,James Douglas; Wilder,James; Roper,David L.; Buchle,Jeff, Low profile chip scale stacking system and method.
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  33. Partridge,Julian; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas, Low profile stacking system and method.
  34. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  35. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
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  52. Tandy,Patrick W., Mold assembly for a package stack via bottom-leaded plastic (BLP) packaging.
  53. Tandy, Patrick W., Mold assembly for a package stack via bottom-leaded plastic (blp) packaging.
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  74. Wehrly, Jr., James Douglas, Stacked modules and method.
  75. Meadows,Paul Milton, Stacking circuit elements.
  76. Rapport,Russell; Cady,James W.; Wilder,James; Roper,David L.; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Stacking system and method.
  77. Roeters,Glen E; Ross,Andrew C, Stacking system and method.
  78. Goodwin, Paul; Cady, James W.; Wehrly, Douglas, Thin module system and method.
  79. Goodwin,Paul, Thin module system and method.
  80. Goodwin,Paul, Thin module system and method.
  81. Gi Bon Cha KR; Hee Joong Suh KR; Chang Kuk Choi KR, Ultra high density integrated circuit BLP stack and method for fabricating the same.
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