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Multi-chip module having interconnect dies 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0484047 (2000-01-18)
발명자 / 주소
  • Crane
  • Jr. Stanford W.
  • Krishnapura Lakshminarasimha
  • Li Yun
  • Behar Moises
  • Fuoco Dan
  • Ahearn Bill
출원인 / 주소
  • Silicon Bandwidth, Inc.
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 6  인용 특허 : 36

초록

A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, su

대표청구항

[ What is claimed is:] [1.]1. A multichip module for housing multiple integrated circuit dies comprising:a housing for holding a plurality of dies;a plurality of integrated circuit dies mounted within said housing;a plurality of interconnect dies mounted within said housing, each of said interconnec

이 특허에 인용된 특허 (36)

  1. Mehr Behrooz (Tempe AZ), Drop-in heat sink.
  2. Gatto Donald F. (Sunrise FL) Milciunas Juan (Ft. Lauderdale FL), Dual electronic component assembly.
  3. Rostoker Michael D. (San Jose CA) Schneider Mark (San Jose CA) Fulcher Edwin (Palo Alto CA), Heat sink for semiconductor device assembly.
  4. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  5. Morrison Paul-David (Round Rock TX), Hermetic semiconductor device having jumper leads.
  6. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  7. Sugano Toshio (Kodaira JPX) Tsukui Seiichiro (Kawagoe JPX), High packing density module board and electronic device having such module board.
  8. Boucard Michel R. J. (Tournefeuille FRX) Francois Thirion C. (Auterive FRX), Housing for an electronic circuit.
  9. Salera Edmond A. (Santa Barbara CA), Hybrid microelectronic circuit package.
  10. Kledzik Kenneth J. (Boise ID), Inherently impedance matched integrated circuit module.
  11. Brownell Michael ; McCutchan Dan ; Xie Hong ; Haley Kevin, Injection molded thermal interface system.
  12. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  13. Papageorge Marc V. (Boca Raton FL) Freyman Bruce J. (Boca Raton FL) Juskey Frank J. (Coral Spring FL) Thome John R. (Palatine IL), Integrated circuit package having a face-to-face IC chip arrangement.
  14. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  15. Krum Alvin L. (Huntington Beach CA) Conklin Charles W. (Huntington Beach CA), Low resistance electrical interconnection for synchronous rectifiers.
  16. Mehr Behrooz (Tempe AZ), Method of making a drop-in heat sink.
  17. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  18. Takiar Hem P. (Fremont CA), Multichip integrated circuit module with crossed bonding wires.
  19. Mohsen Amr (Saratoga CA), Multichip module integrated circuit device having maximum input/output capability.
  20. Spall Edward J. (Manassas VA) Storey Thomas M. (Manassas VA), Multichip module with integrated test circuitry disposed within interposer substrate.
  21. Selinko George J. (Lighthouse Point FL), Non-hermetically sealed stackable chip carrier package.
  22. Ramsey Kenneth C. (Gilbert AZ) Miller William J. (Mesa AZ) Strom William M. (Chandler AZ), Package for mating with a semiconductor die.
  23. Janai Meir I. (Haifa ILX) Orbach Zvi (Haifa ILX), Personalizable multi-chip carrier including removable fuses.
  24. Muehling Richard (Cranston RI), Plastic pin grid array chip carrier.
  25. Kohno Ryuji (Ibaraki JPX) Nishimura Asao (Ushiku JPX) Kitano Makoto (Tsuchiura JPX) Yaguchi Akihiro (Ibaraki JPX) Yoneda Nae (Ibaraki JPX), Plastic-molded-type semiconductor device.
  26. Hashemi Seyed H. (Austin TX) Olla Michael A. (Austin TX) Parker John C. (Round Rock TX), Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template.
  27. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  28. Chance Dudley A. (Newton CT) Davidson Evan E. (Hopewell Junction NY) Dinger Timothy R. (Croton-on-Hudson NY) Goland David B. (Bedford Hills NY) Lapotin David P. (Carmel NY), Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance.
  29. Nagano Junya (Kanagawa JPX), Semiconductor device having an interconnecting circuit board.
  30. Mosley Joseph M. ; Portuondo Maria M., Semiconductor die carrier having a dielectric epoxy between adjacent leads.
  31. Hoffman Paul R. (Modesto CA) Prasad Keshav B. (Santa Clara CA) Caulfield Thomas (Croton Falls NY) Crowley Sean T. (Plano TX), Semiconductor package with chip redistribution interposer.
  32. Carson John C. (Corona del Mar CA) DeCaro Robert E. (San Juan Capistrano CA) Hsu Ying (Huntington Beach CA) Miyake Michael K. (Westminster CA), Stackable modules and multimodular assemblies.
  33. Purdom Gregory W. ; Berecz Endre M., Stacked memory for flight recorders.
  34. Nicewarner ; Jr. Earl R. (Gaithersburg MD), Three-dimensional integrated circuit package.
  35. Moresco Larry L. (San Carlos CA) Horine David A. (Los Altos CA) Wang Wen-Chou V. (Cupertino CA), Three-dimensional multichip module.
  36. Harris David B. (Columbia MD) Karr Scott P. (Columbia MD) Reinhart Stephen J. (Annapolis MD), VLSI integration into a 3-D WSI dual composite module.

이 특허를 인용한 특허 (6)

  1. Sutardja, Sehat; Kao, Vincent; Santo, Hendrick, High performance leadframe in electronic package.
  2. Sutardja, Sehat; Kao, Vincent; Santo, Hendrick, Method for fabricating high performance leadframe in electronic package.
  3. Tan, Swee Seng Eric; Lee, Choon Kuan, Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice.
  4. Kelkar, Nikhil Vishwanath; Liu, Kai, Package leadframe for dual side assembly.
  5. Seng, Eric Tan Swee; Kuan, Lee Choon, Semiconductor device assemblies including face-to-face semiconductor dice and related methods.
  6. Seng, Eric Tan Swee; Kuan, Lee Choon, Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies.
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