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Intermediate-grain reconfigurable processing device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0292497 (1999-04-15)
발명자 / 주소
  • DeHon Andre
  • Mirsky Ethan
  • Knight
  • Jr. Thomas F.
출원인 / 주소
  • Massachusetts Institute of Technology
대리인 / 주소
    Hamilton, Brook, Smith & Reynolds, P.C.
인용정보 피인용 횟수 : 122  인용 특허 : 24

초록

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for op

대표청구항

[ We claim:] [1.]1. A programmable integrated circuit comprising:logic units which perform operations on data in response to instructions of a defined set of instructions;memories which store and retrieve data in response to received addresses;a configurable interconnect which provides signal transm

이 특허에 인용된 특허 (24)

  1. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  2. Duval James R. (Shrewsbury MA) Hunt Thomas E. (Brookline NH) Peterson Kevin R. (Stow MA), Configurable data path arrangement for resolving data type incompatibility.
  3. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  4. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  5. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
  6. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  7. McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.
  8. Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
  9. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  10. Grondalski Robert S. (Maynard MA), Mechanism for broadcasting data in a massively parallell array processing system.
  11. Heil Thomas F. (Easley SC) Robbins Daniel C. (Easley SC) McDonald Edward A. (Lexington SC), Method and apparatus for decoding bus master arbitration levels to optimize memory transfers.
  12. Guyer James M. (Marlboro MA) Epstein David I. (Framingham MA) Keating David L. (Holliston MA) Anderson Walker (Arlington MA) Veres James E. (Framingham MA) Kimmens Harold R. (Hudson MA), Method and apparatus for enhancing the operation of a data processing system.
  13. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.
  14. Zak Robert C. (Lexington MA) Leiserson Charles E. (Winchester MA) Kuzmaul Bradley C. (Waltham MA) Yang Shaw-Wen (Waltham MA) Hillis W. Daniel (Cambridge MA) Douglas David C. (Concord MA) Potter David, Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a p.
  15. Gifford David K. (Cambridge MA), Parallel processing system with processor array having memory system included in system memory.
  16. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  17. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
  18. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  19. Pombo Raul (Plantation FL) Borras Jaime (Hialeah FL) Bron Michel (Lausanne CHX), Protection circuit for a microprocessor.
  20. Saccardi Raymond J. (Laurel MD), Reconfigurable pipelined processor.
  21. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  22. Fijany Amir (Sherman Oaks CA) Bejczy Antal K. (Pasadena CA), Special purpose parallel computer architecture for real-time control and simulation in robotic applications.
  23. Gephardt Douglas D. ; Stewart Brett B. ; Wisor Rita M. ; Belt Steven L. ; Dutton Drew J., System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the inf.
  24. Papadopoulos Gregory M. (Arlington MA) Culler David E. (Boston MA) Arvind (Arlington MA), Tagged token data processing system with operand matching in activation frames.

이 특허를 인용한 특허 (122)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  11. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  13. Master, Paul L.; Watson, John, Apparatus, method and system for generating a unique hardware adaptation inseparable from correspondingly unique content.
  14. Master,Paul L.; Watson,John, Apparatus, method and system for generating a unique hardware adaptation inseparable from correspondingly unique content.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  20. Hogenauer, Eugene B., Arithmetic node including general digital signal processing functions for an adaptive computing machine.
  21. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  22. de Waal, Abraham B.; Diard, Franck R., Automatic quality testing of multimedia rendering by software drivers.
  23. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
  24. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
  25. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  26. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  27. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
  28. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba, Consumer product distribution in the embedded system market.
  29. Wilkinson, III,Hugh M.; Rosenbluth,Mark B.; Adiletta,Matthew J.; Bernstein,Debra; Wolrich,Gilbert, Context pipelines.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  31. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  32. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  33. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
  34. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  35. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
  36. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
  37. Osann, Jr., Robert; Hallinan, Patrick; Lee, Jung; Mukund, Shridhar, Depopulated programmable logic array.
  38. Osann, Jr.,Robert; Hallinan,Patrick; Lee,Jung; Mukund,Shridhar, Depopulated programmable logic array.
  39. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
  40. Sutou, Shin-ichi, Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network.
  41. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  42. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  43. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  44. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  45. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
  46. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  47. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  48. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  49. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  50. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  51. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James, Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.
  52. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  53. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
  54. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  55. Stewart,Malcolm; Giernalcyzk,Eric; Beriault,Richard, Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies.
  56. Heidari-Bateni, Ghobad; Sambhwani, Sharad D., Internal synchronization control for adaptive integrated circuitry.
  57. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  58. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  59. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  60. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  61. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  62. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  63. Mitchler, Dennis Wayne, Low-power reconfigurable hearing instrument.
  64. Mitchler,Dennis Wayne, Low-power reconfigurable hearing instrument.
  65. Coulman, Paula Kristine; Dhong, Sang Hoo; Flachs, Brian King; Hofstee, Harm Peter; Park, Jaehong; Posluszny, Stephen Douglas; Silberman, Joel Abraham; Takahashi, Osamu, Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays.
  66. Mansingh, Sanjay; Patkar, Niteen; Van Dyke, Korbin; Hale, Stephen; Tovey, Dee; Patwa, Nital; Purcell, Stephen C., Method and apparatus of configurable processing.
  67. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  68. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
  69. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  70. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  71. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  72. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  73. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  74. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  75. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  76. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  77. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  78. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  79. Master, Paul L.; Scheuermann, W. James, Method and system for reducing the time-to-market concerns for embedded system design.
  80. Vorbach, Martin, Method for debugging reconfigurable architectures.
  81. Vorbach, Martin, Method for debugging reconfigurable architectures.
  82. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
  83. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
  84. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
  85. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  86. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  87. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  88. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
  89. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  90. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  91. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  92. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  93. Tabaru, Tsuguchika, Multiplexing auxiliary processing element and semiconductor integrated circuit.
  94. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  95. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  96. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  97. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  98. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  99. Pires Dos Reis Moreira, Orlando Miguel; Augusteijn, Alexander; De Oliveira Kastrup Pereira, Bernardo; Yedema, Wim Feike Dominicus; Hoogendijk, Paul Ferenc; Mallon, Willem Charles, Processing system including a reconfigurable channel infrastructure comprising a control chain with combination elements for each processing element and a programmable switch between each pair of neighboring processing elements for efficient clustering of processing elements.
  100. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  101. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  102. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  103. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  104. Ozawa,Kunihiko, Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system.
  105. Vorbach, Martin, Reconfigurable elements.
  106. Vorbach, Martin, Reconfigurable elements.
  107. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  108. John Morelli ; H. Richard Kendall, Reconfigurable logic for a computer.
  109. Vorbach, Martin, Reconfigurable sequencer structure.
  110. Vorbach, Martin, Reconfigurable sequencer structure.
  111. Vorbach, Martin, Reconfigurable sequencer structure.
  112. Vorbach, Martin, Reconfigurable sequencer structure.
  113. Vorbach, Martin; Bretz, Daniel, Router.
  114. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  115. Master,Paul L.; Watson,John, Storage and delivery of device features.
  116. Stewart,Malcolm; Giernalczyk,Eric; Beriault,Richard, Switch complex selectively coupling input and output of a node in two-dimensional array to four ports and using four switches coupling among ports.
  117. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  118. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  119. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  120. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  121. Bruner, Curtis H.; Squires, Christopher J., Transfer of object memory references in a data storage device.
  122. Goldin, Alexander, Two stage frequency subband decomposition.
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