초록 ▼

The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity for simultaneous dual polarity/dual beam signals by phased-array modules. Additionally, an improved phase shifter design that is smaller and requiring fewer electro

The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity for simultaneous dual polarity/dual beam signals by phased-array modules. Additionally, an improved phase shifter design that is smaller and requiring fewer electronic components than prior art phase shifters is disclosed. In particular, the phase shifter requires only a single control line for each stage of the phase shifter.

대표청구항 ▼

[ The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:] [1.]1. An improved MMIC dual polarization amplifier architecture for use in a phased array antenna comprising:(a) a first amplifier for amplifying a first received signal, said first am

[ The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:] [1.]1. An improved MMIC dual polarization amplifier architecture for use in a phased array antenna comprising:(a) a first amplifier for amplifying a first received signal, said first amplifier providing a first amplified output signal and having:(i) a first amplification stage including a first transistor, said first amplification stage receiving said first received signal;(ii) a second amplification stage connected to said first amplification stage, said second amplification stage including a second transistor;(iii) a power filter comprising a series L, shunt C bypass network for providing broadband bias line isolation, said power filter connected to said second amplification stage;(iv) a first source feedback inductor connected to the source of said first transistor;(v) a second source feedback inductor connected to the source of said second transistor; and(vi) means for series bias of said first transistor and said second transistor, said means for series bias connected between the source of said second transistor and the drain of said first transistor;(b) a second amplifier for amplifying a second received signal, said second received signal being substantially orthogonal to said first received signal, said second amplifier providing a second amplified output signal; and(c) a coupler for receiving said first and second amplified output signals and outputting a left-hand circularly polarized signal and a right-hand circularly polarized signal.