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Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0099192 (1998-06-17)
발명자 / 주소
  • Fernando John S.
  • Thurnhofer Stefan
출원인 / 주소
  • Agere Systems Guardian Corp.
대리인 / 주소
    Synnestvedt & Lechner LLP
인용정보 피인용 횟수 : 219  인용 특허 : 12

초록 ▼

A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching bet

대표청구항 ▼

[ What is claimed is:] [1.]1. An integrated circuit having a single digital processor for switching between different modes of operation, said single digital processor comprising:a first instruction pipeline comprising a first fetch stage, a first decoder stage, and a first execute stage, for proces

이 특허에 인용된 특허 (12)

  1. Chow Hwang-Cherng,TWX, CMOS output buffer with reduced L-DI/DT noise.
    상세보기
  2. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
    상세보기
  3. Kiyohara Tokuzo (Osaka JPX) Deguchi Masashi (Nara JPX), Loosely coupled pipeline processor.
    상세보기
  4. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
    상세보기
  5. Kan Takashi (Kanagawa JPX), Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system cont.
    상세보기
  6. Gifford David K. (Cambridge MA), Parallel processing system with processor array having SIMD/MIMD instruction processing.
    상세보기
  7. Gifford David K. (Cambridge MA), Parallel processing system with processor array having memory system included in system memory.
    상세보기
  8. Watanabe Takao (Inagi JPX) Nakagawa Tetsuya (Koganei JPX) Nakagome Yoshinobu (Hamura JPX), Parallel processor having decoder for selecting switch from the group of switches and concurrently inputting MIMD instru.
    상세보기
  9. Christian Ronald W. (Indianapolis IN) Kutzavitch Walter G. (Indianapolis IN), Power supply circuit for a data processor.
    상세보기
  10. McLaughlin Donald L. (Newtown Square PA) Streiber Ronald W. (Norristown PA), Reducing power consumption in calculators.
    상세보기
  11. Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).
    상세보기
  12. Suzuki Masahiro (Hanno JPX) Nozaki Kenzi (Hanno JPX) Hosoya Toshiyuki (Hanno JPX) Suzuki Takashi (Hanno JPX) Basaki Yuzi (Iruma JPX) Kozima Mitiyo (Kawagoe JPX) Matsuura Naosuke (Naruto JPX), Styrene derivatives and salts thereof.
    상세보기

이 특허를 인용한 특허 (219)

  1. Abdallah, Mohammad, Accelerated code optimizer for a multiengine microprocessor.
    상세보기
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
    상세보기
  8. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
    상세보기
  9. Abdallah, Mohammad A., Apparatus and method for processing an instruction matrix specifying parallel and dependent operations.
    상세보기
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  16. Lyuh, Chun-Gi; Suk, Jung-Hee; Chun, Ik-Jae; Heo, Se-Wan; Roh, Tae-Moon; Kim, Jong-Dae, Arithmetic units responsive to common control signal to generate signals to selectors for selecting instructions from among respective program memories for SIMD / MIMD processing control.
    상세보기
  17. Wolrich,Gilbert; Adiletta,Matthew J.; Wheeler,William R.; Bernstein,Debra; Hooper,Donald F., Branch instruction for processor with branching dependent on a specified bit in a register.
    상세보기
  18. Bernstein,Debra; Kornfeld,Serge; Johnson,Desmond R.; Hooper,Donald F.; Guilford,James D.; Muratori,Richard D., Breakpoint method for parallel hardware threads in multithreaded processor.
    상세보기
  19. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J., Bus interface with a first-in-first-out memory.
    상세보기
  20. Kanapathippillai,Ruban; Ganapathy,Kumar; Nguyen,Thu; Venkatraman,Siva; Philhower, III,Earle F.; Mehta,Manoj; Malich,Kenneth, Bus state keepers.
    상세보기
  21. Abdallah, Mohammad A., Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer.
    상세보기
  22. Zhou, Xu; Huang, Lin; Xie, Michael, Circuits and methods for efficient data transfer in a virus co-processing system.
    상세보기
  23. Zhou, Xu; Huang, Lin; Xie, Michael, Circuits and methods for operating a virus co-processor.
    상세보기
  24. Wolrich,Gilbert; Bernstein,Debra; Adiletta,Matthew J., Communication between processors.
    상세보기
  25. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
    상세보기
  26. O'Brien, John Kevin Patrick; O'Brien, Kathryn M.; Prener, Daniel Arthur, Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data.
    상세보기
  27. Shi, Fuqiang; Staszewski, Roman; Staszewski, Robert B., Computation parallelization in software reconfigurable all digital phase lock loop.
    상세보기
  28. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
    상세보기
  29. Tu, Yifeng, Configurable multicore network processor.
    상세보기
  30. Lee, Tzu-Fang; Lin, Chien-Hong; Liang, Jing-Shan; Wang, Chi-Lung, Configurable processing apparatus and system thereof.
    상세보기
  31. Wilkinson, III,Hugh M.; Rosenbluth,Mark B.; Adiletta,Matthew J.; Bernstein,Debra; Wolrich,Gilbert, Context pipelines.
    상세보기
  32. Guo, Zhi; Lu, Hongbin; Zhou, Xu; Huang, Lin; Xie, Michael, Context-aware pattern matching accelerator.
    상세보기
  33. Guo, Zhi; Lu, Hongbin; Zhou, Xu; Huang, Lin; Xie, Michael, Context-aware pattern matching accelerator.
    상세보기
  34. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Adiletta,Matthew J., Control mechanisms for enqueue and dequeue operations in a pipelined network processor.
    상세보기
  35. Goto,Harutaka, Data processing apparatus and method for controlling staged multi-pipeline processing.
    상세보기
  36. Orion, Luc; Airaud, Cédric Denis Robert; Alvarez-Heredia, Boris Sira, Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction.
    상세보기
  37. Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra; Adiletta, Matthew J., Data transfer mechanism using unidirectional pull bus and push bus.
    상세보기
  38. Abdallah, Mohammad, Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines.
    상세보기
  39. Glossner, III,Clair John; Hokenek,Erdem; Meltzer,David; Moudgill,Mayan, Digital signal processor with cascaded SIMD organization.
    상세보기
  40. Wolrich,Gilbert; Adiletta,Matthew I.; Wheeler,William; Bernstein,Debra; Hooper,Donald, Double shift instruction for micro engine used in multithreaded parallel processor architecture.
    상세보기
  41. Zhou, Xu; Huang, Lin; Xie, Michael, Efficient data transfer in a virus co-processing system.
    상세보기
  42. Zhou, Xu; Huang, Lin; Xie, Michael, Efficient data transfer in a virus co-processing system.
    상세보기
  43. Zhou, Xu; Huang, Lin; Xie, Michael, Efficient data transfer in a virus co-processing system.
    상세보기
  44. Yang,Yil Suk; Roh,Tae Moon; Lee,Dae Woo; Lee,Sang Heung; Kim,Jong Dae, Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type.
    상세보기
  45. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
    상세보기
  46. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
    상세보기
  47. Chen, Lin, Executing subroutines in a multi-threaded processing system.
    상세보기
  48. Omtzigt, Erwinus Theodorus Leonardus, Execution engine for executing single assignment programs with affine dependencies.
    상세보기
  49. Omtzigt, Erwinus Theodorus Leonardus, Execution engine for executing single assignment programs with affine dependencies.
    상세보기
  50. Omtzigt, Erwinus Theodorus Leonardus, Execution engine for executing single assignment programs with affine dependencies.
    상세보기
  51. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
    상세보기
  52. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
    상세보기
  53. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
    상세보기
  54. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  55. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  56. Hooper,Donald F.; Wilde,Myles J.; Adiletta,Matthew J.; Wolrich,Gilbert, Flow control in a network environment.
    상세보기
  57. Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra; Sweeney, John; Guilford, James D., Free list and ring data structure management.
    상세보기
  58. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Sweeney,John; Guilford,James D., Free list and ring data structure management.
    상세보기
  59. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  60. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  61. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  62. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  63. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  64. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  65. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  66. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  67. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  68. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  69. Parsons, Scott; Taylor, David E.; Schuehler, David Vincent; Franklin, Mark A.; Chamberlain, Roger D., High speed processing of financial information using FPGA devices.
    상세보기
  70. Kanapathippillai,Ruban; Ganapathy,Kumar; Nguyen,Thu; Venkatraman,Siva; Philhower, III,Earle F.; Mehta,Manoj; Malich,Kenneth, IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic.
    상세보기
  71. Colavin,Osvaldo M., Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address.
    상세보기
  72. Chamberlain, Roger D.; Brink, Benjamin M.; White, Jason R.; Franklin, Mark A.; Cytron, Ron K., Intelligent data storage and processing using FPGA devices.
    상세보기
  73. Chamberlain, Roger D.; Franklin, Mark Allen; Indeck, Ronald S.; Cytron, Ron K.; Cholleti, Sharath R., Intelligent data storage and processing using FPGA devices.
    상세보기
  74. Chamberlain, Roger D.; Franklin, Mark Allen; Indeck, Ronald S.; Cytron, Ron K.; Cholleti, Sharath R., Intelligent data storage and processing using FPGA devices.
    상세보기
  75. Chamberlain, Roger D.; Franklin, Mark Allen; Indeck, Ronald S.; Cytron, Ron K.; Cholleti, Sharath R., Intelligent data storage and processing using FPGA devices.
    상세보기
  76. Chamberlain, Roger D.; Franklin, Mark Allen; Indeck, Ronald S.; Cytron, Ron K.; Cholleti, Sharath R., Intelligent data storage and processing using FPGA devices.
    상세보기
  77. Parsons, Scott; Taylor, David E.; Indeck, Ronald S., Intelligent feed switch.
    상세보기
  78. Abdallah, Mohammad, Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines.
    상세보기
  79. de Jong,Eduard K., Interleaved data and instruction streams for application program obfuscation.
    상세보기
  80. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  81. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  82. Tran, Thang, Managing power of thread pipelines according to clock frequency and voltage specified in thread registers.
    상세보기
  83. Rosenbluth,Mark B.; Wolrich,Gilbert; Bernstein,Debra, Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment.
    상세보기
  84. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Memory access consolidation for SIMD processing elements using transaction identifiers.
    상세보기
  85. Wheeler,William R.; Burres,Bradley; Adiletta,Matthew J.; Wolrich,Gilbert, Memory controller for processor having multiple multithreaded programmable units.
    상세보기
  86. Wheeler, William R.; Burres, Bradley; Adiletta, Matthew J.; Wolrich, Gilbert, Memory controllers for processor having multiple programmable units.
    상세보기
  87. Abdallah, Mohammad, Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines.
    상세보기
  88. Wolrich, Gilbert; Rosenbluth, Mark B., Memory interleaving.
    상세보기
  89. Wolrich,Gilbert; Rosenbluth,Mark B.; Adiletta,Matthew J., Memory interleaving.
    상세보기
  90. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  91. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  92. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  93. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  94. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  95. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Memory mapping in a processor having multiple programmable units.
    상세보기
  96. Indeck, Ronald S.; Cytron, Ron Kaplan; Franklin, Mark Allen, Method and apparatus for adjustable data matching.
    상세보기
  97. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J.; Hooper, Donald F., Method and apparatus for gigabit packet assignment for multithreaded packet processing.
    상세보기
  98. Taylor, David E.; Parsons, Scott; Whatley, Jeremy Walter; Bradley, Richard; Gyang, Kwame; DeWulf, Michael, Method and apparatus for high-speed processing of financial market depth data.
    상세보기
  99. Taylor, David E.; Parsons, Scott; Whatley, Jeremy Walter; Bradley, Richard; Gyang, Kwame; DeWulf, Michael, Method and apparatus for high-speed processing of financial market depth data.
    상세보기
  100. Taylor, David E.; Parsons, Scott; Whatley, Jeremy Walter; Bradley, Richard; Gyang, Kwame; DeWulf, Michael, Method and apparatus for high-speed processing of financial market depth data.
    상세보기
  101. Taylor, David E.; Parsons, Scott; Schuehler, David Vincent; Strader, Todd Alan; Eder, Ryan L., Method and apparatus for low latency data distribution.
    상세보기
  102. Taylor, David; Parsons, Scott, Method and apparatus for managing orders in financial markets.
    상세보기
  103. Buhler, Jeremy Daniel; Chamberlain, Roger Dean; Franklin, Mark Allen; Gyang, Kwame; Jacob, Arpith Chacko; Krishnamurthy, Praveen; Lancaster, Joseph Marion, Method and apparatus for performing similarity searching.
    상세보기
  104. Buhler, Jeremy Daniel; Chamberlain, Roger Dean; Franklin, Mark Allen; Gyang, Kwame; Jacob, Arpith Chacko; Krishnamurthy, Praveen; Lancaster, Joseph Marion, Method and apparatus for performing similarity searching.
    상세보기
  105. Indeck, Ronald S.; Cytron, Ron Kaplan; Franklin, Mark Allen, Method and apparatus for processing streaming data using programmable logic.
    상세보기
  106. Wolrich, Gilbert; Adiletta, Matthew J.; Wheeler, William, Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set.
    상세보기
  107. Berenbaum, Alan David; Heintze, Nevin; Jeremiassen, Tor E.; Kaxiras, Stefanos, Method and apparatus for releasing functional units in a multithreaded VLIW processor.
    상세보기
  108. Kuo,Chen Chi; Lakshmanamurthy,Sridhar; Natarajan,Rohit; Liu,Kin Yip; Chandra,Prashant R.; Guilford,James D., Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches.
    상세보기
  109. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
    상세보기
  110. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
    상세보기
  111. Indeck, Ronald S.; Indeck, David Mark; Singla, Naveen; Taylor, David E., Method and system for high performance integration, processing and searching of structured and unstructured data.
    상세보기
  112. Indeck, Ronald S.; Indeck, David Mark, Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors.
    상세보기
  113. Indeck, Ronald S.; Indeck, David Mark, Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors.
    상세보기
  114. Indeck, Ronald S.; Singla, Naveen; Taylor, David E., Method and system for high performance pattern indexing.
    상세보기
  115. Singla, Naveen; Parsons, Scott; Franklin, Mark A.; Taylor, David E., Method and system for high speed options pricing.
    상세보기
  116. Taylor, David E.; Singla, Naveen; Brodie, Benjamin C.; McVicar, Nathaniel Sutton; Thiel, Justin Ryan; Indeck, Ronald S., Method and system for low latency basket calculation.
    상세보기
  117. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  118. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  119. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  120. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  121. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  122. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  123. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  124. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  125. Abdallah, Mohammad, Method for dependency broadcasting through a block organized source view data structure.
    상세보기
  126. Abdallah, Mohammad, Method for dependency broadcasting through a source organized source view data structure.
    상세보기
  127. Abdallah, Mohammad, Method for emulating a guest centralized flag architecture by using a native distributed flag architecture.
    상세보기
  128. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
    상세보기
  129. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
    상세보기
  130. Abdallah, Mohammad, Method for implementing a reduced size register view data structure in a microprocessor.
    상세보기
  131. Abdallah, Mohammad A., Method for implementing a reduced size register view data structure in a microprocessor.
    상세보기
  132. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
    상세보기
  133. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
    상세보기
  134. Abdallah, Mohammad, Method for populating a source view data structure by using register template snapshots.
    상세보기
  135. Abdallah, Mohammad, Method for populating and instruction view data structure by using register template snapshots.
    상세보기
  136. Abdallah, Mohammad, Method for populating register view data structure by using register template snapshots.
    상세보기
  137. Blott, Michaela; English, Thomas B.; Vissers, Kornelis A., Method of and device for processing data using a pipeline of processing blocks.
    상세보기
  138. Sasanka, Ruchira, Method, apparatus, system creating, executing and terminating mini-threads.
    상세보기
  139. Pechanek, Gerald George; Barry, Edwin Franklin; Stojancic, Mihailo, Methods and apparatus for independent processor node operations in a SIMD array processor.
    상세보기
  140. Noyes, Harold B; Brown, David R., Methods and apparatuses for reducing power consumption in a pattern recognition processor.
    상세보기
  141. Noyes, Harold B; Brown, David R., Methods and apparatuses for reducing power consumption in a pattern recognition processor.
    상세보기
  142. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
    상세보기
  143. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
    상세보기
  144. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
    상세보기
  145. Abdallah, Mohammad; Groen, Ankur; Gunadi, Erika; Singh, Mandeep; Rao, Ravishankar, Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation.
    상세보기
  146. Bernstein,Debra; Hooper,Donald F.; Adiletta,Matthew J.; Wolrich,Gilbert; Wheeler,William, Microengine for parallel processor architecture.
    상세보기
  147. DeLano,Eric, Multi-cluster processor for processing instructions of one or more instruction threads.
    상세보기
  148. Hooper,Donald F.; Adiletta,Matthew J., Multi-threaded round-robin receive for fast network port.
    상세보기
  149. Hooper,Donald F.; Adiletta,Matthew J.; Wolrich,Gilbert M., Multi-threaded sequenced receive for fast network port stream of packets.
    상세보기
  150. Tran, Thang, Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture.
    상세보기
  151. Sun, Weiyun; Berg, Stefan G.; Kim, Donglok; Kim, Yongmin, Multimedia instruction set for wide data paths.
    상세보기
  152. Borianne,Paul Louis, Multipath processor with dedicated buses.
    상세보기
  153. Hooper,Donald F.; Kalkunte,Suresh, Multiple calendar schedule reservation structure and method.
    상세보기
  154. de Jong,Eduard K., Multiple instruction dispatch tables for application program obfuscation.
    상세보기
  155. Rosenbluth,Mark B.; Wolrich,Gilbert; Bernstein,Debra; Wilde,Myles J.; Adiletta,Matthew J., Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms.
    상세보기
  156. Sasagawa,Yukihiro, Multiprocessor system and program optimizing method.
    상세보기
  157. Hooper,Donald F.; Hirnak,Stephanie L., Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method.
    상세보기
  158. Gosior,Jason; Broughton,Colin; Jacobsen,Phillip; Sobota,John, Multithread embedded processor with input/output capability.
    상세보기
  159. Rosenbluth,Mark B.; Wolrich,Gilbert; Bernstein,Debra, Multithreaded microprocessor with register allocation based on number of active threads.
    상세보기
  160. Tran, Thang, Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines.
    상세보기
  161. de Jong,Eduard K., Non-linear execution of application program instructions for application program obfuscation.
    상세보기
  162. Parsons, Scott; Taylor, David E.; Indeck, Ronald S., Offload processing of data packets containing financial market data.
    상세보기
  163. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  164. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  165. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  166. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  167. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  168. Zhou, Xu; Huang, Lin; Xie, Michael, Operation of a dual instruction pipe virus co-processor.
    상세보기
  169. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J.; Wheeler, William, Parallel multi-threaded processing.
    상세보기
  170. Adiletta, Matthew J.; Wolrich, Gilbert; Wheeler, William, Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode.
    상세보기
  171. Sueyoshi, Toshinori; Iida, Masahiro; Nakano, Mitsutaka; Senoue, Fumiaki; Mizumoto, Katsuya, Parallel operation device allowing efficient parallel operational processing.
    상세보기
  172. Wilkinson, III, Hugh M.; Adiletta, Matthew J.; Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra; Wilde, Myles J., Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section.
    상세보기
  173. de Jong,Eduard K., Permutation of opcode values for application program obfuscation.
    상세보기
  174. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J., Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch.
    상세보기
  175. Hooper,Donald F.; Rosenbluth,Mark B.; Wolrich,Gilbert; Adiletta,Matthew J.; Wilkinson, III,Hugh M.; Kushlis,Robert J., Processing a data packet.
    상세보기
  176. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra, Processing data packets.
    상세보기
  177. Wilkinson, III,Hugh M.; Adiletta,Matthew J.; Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Wilde,Myles J., Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access.
    상세보기
  178. Mejdrich, Eric Oliver; Muff, Adam James; Tubbs, Matthew Ray, Processing unit incorporating vectorizable execution unit.
    상세보기
  179. Seo, Woong; Cho, Yeon-Gon; Ryu, Soo-Jung, Processor and method for dynamically allocating processing elements to front end units using a plurality of registers.
    상세보기
  180. Wolrich, Gilbert; Adiletta, Matthew; Wheeler, William R., Processor having a dedicated hash unit integrated within.
    상세보기
  181. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
    상세보기
  182. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew; Wheeler, William, Providing real-time control data for a network processor.
    상세보기
  183. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra, Queue array caching in network devices.
    상세보기
  184. Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra, Queue arrays in network devices.
    상세보기
  185. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Hooper,Donald F., Queue management.
    상세보기
  186. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
    상세보기
  187. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
    상세보기
  188. Wolrich, Gilbert; Adiletta, Matthew J.; Wheeler, William R.; Bernstein, Debra; Hooper, Donald F., Register set used in multithreaded parallel processor architecture.
    상세보기
  189. Wolrich, Gilbert; Adiletta, Matthew J; Wheeler, William R.; Bernstein, Debra; Hooper, Donald F., Register set used in multithreaded parallel processor architecture.
    상세보기
  190. Wolrich,Gilbert; Rosenbluth,Mark B.; Bernstein,Debra; Adiletta,Matthew J.; Wilkinson, III,Hugh M., Registers for data transfers.
    상세보기
  191. de Jong, Eduard K., Rendering and encryption engine for application program obfuscation.
    상세보기
  192. Colavin, Osvaldo M., Replicating opcode to other lanes and modifying argument register to others in vector portion for parallel operation.
    상세보기
  193. Wheeler,William R.; Burres,Bradley; Adiletta,Matthew J.; Wolrich,Gilbert, SDRAM controller for parallel processor architecture.
    상세보기
  194. Canella, Alberto; Fugger, Paul; Nossing, Gerhard, SIMD processor with a subroutine control unit.
    상세보기
  195. Kalkunte,Suresh S.; Hooper,Donald F., Scheduling system for transmission of cells to ATM virtual circuits and DSL ports.
    상세보기
  196. Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew, Scratchpad memory.
    상세보기
  197. Park,Gi ho, Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating.
    상세보기
  198. Abdallah, Mohammad, Single cycle multi-branch prediction including shadow cache for early far branch prediction.
    상세보기
  199. Rosenbluth, Mark B.; Wolrich, Gilbert; Bernstein, Debra, Software controlled content addressable memory in a general purpose execution datapath.
    상세보기
  200. Rosenbluth,Mark B.; Wolrich,Gilbert; Bernstein,Debra, Software controlled content addressable memory in a general purpose execution datapath.
    상세보기
  201. Nelson, S. Craig, Split latency decoding.
    상세보기
  202. Adiletta,Matthew J.; Wheeler,William; Redfield,James; Cutter,Daniel; Wolrich,Gilbert, Sram controller for parallel processor architecture including a read queue and an order queue for handling requests.
    상세보기
  203. Master,Paul L.; Watson,John, Storage and delivery of device features.
    상세보기
  204. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
    상세보기
  205. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
    상세보기
  206. Tran, Thang M., Systems and methods for configuring load/store execution units.
    상세보기
  207. Tran, Thang M., Systems and methods for reconfiguring cache memory.
    상세보기
  208. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
    상세보기
  209. Wolrich,Gilbert; Bernstein,Debra; Hooper,Donald; Adiletta,Matthew J.; Wheeler,William, Thread signaling in multi-threaded processor.
    상세보기
  210. Golla, Robert T.; Brooks, Jeffrey S.; Olson, Christopher H., Thread-based clock enabling in a multi-threaded processor.
    상세보기
  211. Kanapathippillai,Ruban; Ganapathy,Kumar; Nguyen,Thu; Venkatraman,Siva; Philhower, III,Earle F.; Mehta,Manoj; Malich,Kenneth, Unified shared pipeline allowing deactivation of RISC/DSP units for power saving.
    상세보기
  212. Norden, Erik K.; Arnold, Roger D.; Ober, Robert E.; Hastie, Neil S., Variable length instruction pipeline.
    상세보기
  213. Norden,Erik K.; Arnold,Roger D.; Ober,Robert E.; Hastie,Neil S., Variable length instruction pipeline.
    상세보기
  214. Luick, David A., Vector morphing mechanism for multiple processor cores.
    상세보기
  215. Huang, Lin; Zhou, Xu; Xie, Michael, Virus co-processor instructions and methods for using such.
    상세보기
  216. Huang, Lin; Zhou, Xu; Xie, Michael, Virus co-processor instructions and methods for using such.
    상세보기
  217. Huang, Lin; Zhou, Xu; Xie, Michael, Virus co-processor instructions and methods for using such.
    상세보기
  218. Huang, Lin; Zhou, Xu; Xie, Michael, Virus co-processor instructions and methods for using such.
    상세보기
  219. Rosenbluth,Mark B.; Bernstein,Debra; Wolrich,Gilbert, Write queue descriptor count instruction for high speed queuing.
    상세보기

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