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Method and apparatus for maintaining test data during fabrication of a semiconductor wafer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/26
출원번호 US-0471842 (1999-12-23)
발명자 / 주소
  • Weber David M.
출원인 / 주소
  • LSI Logic Corporation
인용정보 피인용 횟수 : 81  인용 특허 : 12

초록 ▼

A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain t

대표청구항 ▼

[ What is claimed is:] [1.]1. A method of fabricating a semiconductor wafer, comprising the steps of:fabricating a number of die on said wafer;fabricating a memory device on said wafer;testing said number of die with a die testing apparatus so as to obtain test data associated with said number of di

이 특허에 인용된 특허 (12)

  1. Takeuchi, Bunzi, Apparatus for scribing semiconductor wafer with laser beam.
    상세보기
  2. Benne Karsten (Ronnenberg DEX) Koop Hermann (Ronnenberg DEX) Schddekopf Hans (Hanover DEX), Disc-shaped information carrier and method of manufacturing it.
    상세보기
  3. Corley Dean (Tempe AZ) Littlebury Hugh W. (Chandler AZ), Integral semiconductor wafer map recording.
    상세보기
  4. Duley Walter W. (98 McClure Drive King City ; Ontario CAX L0G 1K0) Bieler Theodore A. (314 Mill Street Richmond Hill ; Ontario CAX L4C 4B5), Laser etching of foam substrate.
    상세보기
  5. Shinohara Hisato (Sagamihara JPX), Laser scribing method.
    상세보기
  6. Gross David E. (Dripping Springs TX), Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing.
    상세보기
  7. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
    상세보기
  8. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.
    상세보기
  9. Chen Chiou-Feng, Nonvolatile memory with self-aligned floating gate and fabrication process.
    상세보기
  10. Johnson Mark G. ; Lee Thomas H. ; Subramanian Vivek ; Farmwald P. Michael ; Cleeves James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
    상세보기
  11. Wills Kendall S. (Farmers Branch TX) Rodriguez Paul A. (Lewisville TX) Brewer Melvin (Plano TX), Wafer scribe technique using laser by forming polysilicon.
    상세보기
  12. Chen Susan Hsuching ; Shiau Ying ; Lee Chern-Jiann, Watchdog system having data differentiating means for use in monitoring of semiconductor wafer testing line.
    상세보기

이 특허를 인용한 특허 (81)

  1. Smith, Michael John Sebastian; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
    상세보기
  2. Smith, Michael John; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
    상세보기
  3. Beckhart, Gordon Haggott; Conarro, Patrick Rooney; Farivar-Sadri, Kamran Michael, Alignment wafer.
    상세보기
  4. Clougherty, Frances S.; Bayat, Benjamin R., Allocating manufactured devices according to customer specifications.
    상세보기
  5. Clougherty,Frances S.; Bayat,Benjamin R., Allocating manufactured devices according to customer specifications.
    상세보기
  6. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Apparatus for simulating an aspect of a memory circuit.
    상세보기
  7. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Combined signal delay and power saving for use with a plurality of memory circuits.
    상세보기
  8. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
    상세보기
  9. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
    상세보기
  10. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastien; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
    상세보기
  11. Rajan, Suresh Natarajan; Wang, David T., Configurable memory system with interface circuit.
    상세보기
  12. Rajan, Suresh Natarajan; Wang, David T., Configurable multirank memory system with interface circuit.
    상세보기
  13. Rajan, Suresh Natarajan; Schakel, Keith R; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Delaying a signal communicated from a system to at least one of a plurality of memory circuits.
    상세보기
  14. Zohni, Wael O.; Schmidt, William L.; Smith, Michael John Sebastian; Plunkett, Jeremy Matthew, Embossed heat spreader.
    상세보기
  15. Zohni, Wael O.; Schmidt, William; Smith, Michael J. S.; Plunkett, Jeremy Matthew, Embossed heat spreader.
    상세보기
  16. Smith, Michael John Sebastian; Rajan, Suresh Natarajan; Wang, David T, Emulation of abstracted DIMMS using abstracted DRAMS.
    상세보기
  17. Smith, Michael J. S.; Rajan, Suresh Natarajan; Wang, David T., Emulation of abstracted DIMMs using abstracted DRAMs.
    상세보기
  18. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
    상세보기
  19. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
    상세보기
  20. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits.
    상세보기
  21. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit.
    상세보기
  22. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power saving operations during a command-related latency.
    상세보기
  23. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
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  24. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
    상세보기
  25. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation system and method with refresh capabilities.
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  26. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation with power saving capabilities.
    상세보기
  27. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
    상세보기
  28. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
    상세보기
  29. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
    상세보기
  30. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory device with emulated characteristics.
    상세보기
  31. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilites.
    상세보기
  32. Rajan, Suresh N.; Schakel, Keith R; Smith, Michael J. S.; Wang, David T; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
    상세보기
  33. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
    상세보기
  34. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory modules with reliability and serviceability functions.
    상세보기
  35. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
    상세보기
  36. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
    상세보기
  37. Wang, David T.; Rajan, Suresh Natarajan, Memory system for synchronous data transmission.
    상세보기
  38. Smith, Michael J. S.; Rajan, Suresh Natarajan, Memory systems and memory modules.
    상세보기
  39. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory systems and memory modules.
    상세보기
  40. Charlton, David E.; Prak, Sovandy N.; Robinson, Keith E., Method and apparatus for storing failing part locations in a module.
    상세보기
  41. Charlton,David E.; Prak,Sovandy N.; Robinson,Keith E., Method and apparatus for storing failing part locations in a module.
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  42. Fenner, Andreas A.; Larson, Lary R.; Gerrish, Paul F.; Fulton, Daniel E.; Bell, James W.; May, James Thomas, Method and apparatus for wafer-level burn-in.
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  43. Fenner, Andreas A.; Thompson, David L., Method and apparatus for wafer-level burn-in and testing of integrated circuits.
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  44. Fenner, Andreas A.; Thompson, David L., Method and apparatus for wafer-level burn-in and testing of integrated circuits.
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  45. Bradl, Stephan; Holmer, Rainer, Method for producing a semiconductor wafer with rear side identification.
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  46. Chen,Kuei Pao; Lai,Tsan Hsiung, Method of integration testing for packaged electronic components.
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  47. Rajan, Suresh N., Methods and apparatus of stacking DRAMs.
    상세보기
  48. Rajan, Suresh N.; Smith, Michael J. S.; Wang, David T, Methods and apparatus of stacking DRAMs.
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  49. Feng-Yi Yang TW, Microelectronic fabrication die electrical probe apparatus electrical test method providing enhanced microelectronic fabrication die electrical test accuracy and efficiency.
    상세보기
  50. Rajan, Suresh Natarajan; Smith, Michael John, Multi-rank partial width memory modules.
    상세보기
  51. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
    상세보기
  52. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
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  53. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
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  54. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
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  55. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Performing error detection on DRAMs.
    상세보기
  56. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Power management of memory circuits by virtual memory simulation.
    상세보기
  57. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Power saving system and method for use with a plurality of memory circuits.
    상세보기
  58. Ferolito, Philip Arnold; Rosenband, Daniel L.; Wang, David T.; Smith, Michael John Sebastian, Programming of DIMM termination resistance values.
    상세보기
  59. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Refresh management of memory modules.
    상세보기
  60. Makita, Toshiyuki, Semiconductor manufacturing method and semiconductor manufacturing apparatus.
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  61. Raitter, James S., Sequential unique marking.
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  62. Raitter,James S., Sequential unique marking.
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  63. Raitter,James S., Sequential unique marking.
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  64. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a different number of memory circuit devices.
    상세보기
  65. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
    상세보기
  66. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
    상세보기
  67. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a refresh operation latency.
    상세보기
  68. Fjelstad, Joseph C., Stackable low-profile lead frame package.
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  69. Wang, David T.; Rajan, Suresh Natarajan, Stacked DIMM memory interface.
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  70. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits.
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  71. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
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  72. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
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  73. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
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  74. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for power management in memory systems.
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  75. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
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  76. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
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  77. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
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  78. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
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  79. Rajan, Suresh Natarajan, System including memory stacks.
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  80. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
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  81. Wang, David T.; Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
    상세보기

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