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Electrical connections with deformable contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/09
출원번호 US-0653930 (2000-09-01)
발명자 / 주소
  • DiStefano Thomas H.
  • Smith John W.
  • Karavakis Konstantine N.
  • Kovac Zlata
  • Fjelstad Joseph
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik, LLP
인용정보 피인용 횟수 : 23  인용 특허 : 38

초록

An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circu

대표청구항

[ What is claimed is:] [1.]1. An interposer for making connections to electrical contacts on a surface of a microelectronic element, the interposer comprising:(a) a body having a first major surface, said body having horizontal directions parallel to said first major surface defining a horizontal pl

이 특허에 인용된 특허 (38)

  1. Dery Ronald A. (Winston-Salem NC) Jones Warren C. (Winston-Salem NC) Lynn William J. (Groveland MA) Rowlette John R. (Clemmons NC), Anisotropically conductive adhesive composition.
  2. Grabbe Dimitry G. (Middletown PA), Area array connector.
  3. Wiley John P. (Vestal NY), Bondable via.
  4. Clark ; Stephen Larry, Circuit board eyelet.
  5. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
  6. Patraw Nils E. (Redondo Beach CA), Compressive pedestal for microminiature connections.
  7. Casciotti, Albert; Deak, Frederick R.; Rowlette, John R., Conductive gel area array connector.
  8. Patraw Nils E. (Redondo Beach CA), Connector system for coupling to an integrated circuit chip.
  9. Ehrenberg Scott G. (Fishkill NY) Herron L. Wynn (Hopewell Junction NY) Miersch Ekkehard F. (Schoenaich NY DEX) Park Jae (Somers NY) Poetzinger Janet L. (Pleasant Valley NY), Discrete fabrication of multi-layer thin film, wiring structures.
  10. Zifcak Mark S. (Putnam CT) Kosa Bruce G. (Woodstock CT), Electrical circuit board interconnect.
  11. Evans William R. (Clemons NC) Sinisi David B. (Harrisburg PA), Electrical connector for interconnecting arrays of conductive areas.
  12. Difrancesco Louis (Hayward CA), Electrical interconnect using particle enhanced joining of metal surfaces.
  13. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  14. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Electrical socket.
  15. Fletcher David L. (Georgetown KY) Graham Arthur E. (Lexington KY), Electrophoretic insulation of metal circuit board core.
  16. Bindra Perminder S. (South Salem NY) Canfield Dennis A. (Montrose PA) Markovich Voya R. (Endwell NY) McKeveny Jeffrey (Binghamton NY) Ruane Robert E. (Endicott NY) Thomas Edwin L. (Apalachin NY), Encapsulated circuitized power core alignment and lamination.
  17. Dux John B. (Millbrook NY) Poetzinger Janet L. (Pleasant Valley NY) Prestipino Roseanne M. (Beacon NY) Siefering Kevin L. (Cary NC), Fabrication of discrete thin film wiring structures.
  18. Grabbe Dimitry G. (Middletown PA), Field emitter array integrated circuit chip interconnection.
  19. Suzuki Tameyuki (Zushi JPX) Kamakura Takuro (Matsudo JPX), Flexible cicuit substrate with electroconductive adhesive layer and its production.
  20. Grabbe Dimitry G. (Middletown PA), High density electrical connector system.
  21. Ciccio Joseph A. (Winchester MA) Thun Rudolf E. (Carlisle MA) Fardy Harry J. (Chelmsford MA), Integrated circuit device package interconnect means.
  22. Schreiber Christopher M. (Newport Beach CA) Crumly Wiliam R. (Anaheim CA) Hanley Robert B. (Santa Ana CA), Interconnection of opposite sides of a circuit board.
  23. Patraw Nils E. (Redondo Beach CA), Inverted chip carrier.
  24. Burger Henry A. (Tempe AZ) White Harold E. (Scottsdale AZ), Method of fabricating a multilayer circuit board assembly.
  25. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Karavakis Konstantine N. (Cupertino CA) Kovac Zlata (Los Gatos CA) Fjelstad Joseph (Sunnyvale CA), Method of making multilayer circuit.
  26. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of packaging and powering integrated circuit chips and the chip assembly formed thereby.
  27. Walkup William B. (79 Balance Rock Rd. ; Apt. 22 Seymour CT 06483), Multi-chip module connector element and system.
  28. King Michael M. (Vashon WA) Walter Helen J. (Seattle WA), Multi-layer circuit board bonding method utilizing noble metal coated surfaces.
  29. DiStefano Thomas H. (Bronxville NY) Khandros Igor Y. (Peekskill NY) Grube Gary W. (Monroe NY), Multi-layer circuit construction methods with customization features.
  30. Crepeau Philip C. (San Diego CA), Multilayer printed circuit board.
  31. Benarr, Garry M.; Burns, Terry A.; Walker, William J., Pinless connector interposer and method for making the same.
  32. Fuller Timothy J. (Berkeley Heights NJ) Marchetti Joseph R. (Hempfield Township ; Westmoreland County PA) Sanjana Zal N. (Penn Hills Township ; Allegheny County PA), Polyimide modified epoxy resins in aqueous emulsions for lamination and electrodeposition.
  33. Arachtingi James J. (Massapequa Park NY), Process for bonding metals to electrophoretically deposited resin coatings.
  34. Thams Johan-Petter B. (69 ; Grnviksvgen S-161 40 Bromma SEX), Process for coating a metal article on and at an edge.
  35. Kurosawa Keiji (Nagano JPX) Yamamoto Kenji (Nagano JPX) Yamashita Mirsuo (Nagano JPX) Mitsui Hisami (Nagano JPX) Miyabara Ayako (Nagano JPX) Miyagawa Kiyotaka (Suzaka JPX) Imura Takayoshi (Nagano JPX, Process for manufacturing hollow multilayer printed wiring board.
  36. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies having interposer and flexible lead.
  37. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  38. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA) Ringler Daniel R. (Elizabethville PA), Surface mount electrical connector.

이 특허를 인용한 특허 (23)

  1. Hougham, Gareth; McVicker, Gerard; Gu, Xiaoxiong; Kang, Sung K.; Libsch, Frank R.; Liu, Xiao H., Axiocentric scrubbing land grid array contacts and methods for fabrication.
  2. Hougham, Gareth; McVicker, Gerard; Gu, Xiaoxiong; Kang, Sung K.; Libsch, Frank R.; Liu, Xiao H., Axiocentric scrubbing land grid array contacts and methods for fabrication.
  3. Hougham, Gareth; McVicker, Gerard; Gu, Xiaoxiong; Kang, Sung K.; Libsch, Frank R.; Liu, Xiao H., Axiocentric scrubbing land grid array contacts and methods for fabrication.
  4. Hosaka, Taiji; Miyazawa, Masaaki, Binding member for coaxial cable and an electric connector for coaxial cable both using resin solder, and a method of connecting the binding member to coaxial cable or the electric connector.
  5. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung, Chip package.
  6. Shibata, Kiyoshi; Usui, Ryosuke; Inoue, Yasunori, Circuit board and circuit apparatus using the same.
  7. Levante, James J; Johnson, Dennis; Sahakian, Tom, Conductive elastomeric and mechanical pin and contact system.
  8. Champion, Bruce Allen; Millard, Steven Jay; Lin, Bin, Connector system having contact overlapping vias.
  9. Dandl, Christian; Wollitzer, Michael; Maiwälder, Armin, Contact spring.
  10. Hosaka, Taiji; Miyazawa, Masaaki, Electric contact and an electric connector both using resin solder and a method of connecting them to a printed circuit board.
  11. Hosaka, Taiji; Miyazawa, Masaaki, Electric contact and an electric connector both using resin solder and a method of connecting them to a printed circuit board.
  12. Mason, Jeffrey Walter; Alden, III, Wayne Stewart, Electrical interconnect device.
  13. Mason, Jeffery Walter; Alden, III, Wayne Stewart, Electrical interconnect device employing an array of conductive elastomer columns.
  14. Self,Bob J.; Logelin,Donald M.; Wardwell,Robert H., High density interconnect.
  15. Rokugawa, Akio; Sasaki, Masayuki; Matsuda, Yuichi, Insulated multilayered substrate having connecting leads for mounting a semiconductor element thereon.
  16. Hougham,Gareth G; Fogel,Keith E; Rosner,Joanna; Lauro,Paul A; Goma,Sherif; Zinter, Jr.,Joseph, Interposer with electrical contact button and method.
  17. Hougham, Gareth G; Fogel, Keith E; Rosner, Joanna; Lauro, Paul A; Goma, Sherif; Zinter, Jr., Joseph, Method for fabricating electrical contact buttons.
  18. Lu You ; Steve Avanzino ; Fei Wang, Method for preventing damage of low-k dielectrics during patterning.
  19. Shibata, Kiyoshi; Usui, Ryosuke; Inoue, Yasunori, Method of manufacturing the circuit apparatus, method of manufacturing the circuit board, and method of manufacturing the circuit device.
  20. Rokugawa, Akio; Sasaki, Masayuki; Matsuda, Yuichi, Multilayered substrate for semiconductor device and method of manufacturing same.
  21. Yamashita, Takahiro; Watanabe, Hiroyuki; Tsukada, Kiyotaka; Ido, Michio; Nakao, Morio, Printed wiring board having a solder pad and a method for manufacturing the same.
  22. Cheng,David C. H., Process of fabricating conductive column.
  23. Wakashima, Yoshiaki; Fukutomi, Naoki; Suzuki, Kazuhisa; Funaki, Takeshi, Substrate for use in package of semiconductor device, semiconductor package using the substrate, and methods for manufacturing the substrate and the semiconductor package.
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