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Multilevel interconnect structure with low-k dielectric and method of fabricating the structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/476.3
출원번호 US-0375561 (1999-08-17)
발명자 / 주소
  • Ahn Kie Y.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dickstein Shapiro Morin & Oshinsky LLP
인용정보 피인용 횟수 : 54  인용 특허 : 3

초록

A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openin

대표청구항

[ What is claimed is:] [1.]1. A method of fabricating a semiconductor interconnect structure comprising the steps of:depositing a layer of photoresist on a substrate assembly; etching the photoresist layer to form a plurality of openings;depositing a metal layer on the photoresist layer to fill the

이 특허에 인용된 특허 (3)

  1. Buynoski Matthew S., Low dielectric semiconductor device with rigid lined interconnection system.
  2. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.
  3. Havemann Robert H. (Plano TX) Jeng Shin-puu (Plano TX), Multilevel interconnect structure with air gaps formed between metal leads.

이 특허를 인용한 특허 (54)

  1. Chang, Ting-Chang; Mor, Yi-Shien; Liu, Po-Tsun, Air gap semiconductor structure and method of manufacture.
  2. Gabric,Zvonimir; Pamler,Werner; Schwarzl,Siegfried, Arrangement of microstructures.
  3. Farrar,Paul A.; Geusic,Joseph, Buried conductor patterns formed by surface transformation of empty spaces in solid state materials.
  4. Downey,Stephen; Harris,Edward; Merchant,Sailesh, Capacitor for integration with copper damascene processes and a method of manufacture therefore.
  5. Donohue,Hilke, Depositing a tantalum film.
  6. Towle, Steven N., Dual damascene process using a low k interlayer for forming vias and trenches.
  7. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  8. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  9. Ahn, Kie Y.; Forbes, Leonard, Films deposited at glancing incidence for multilevel metallization.
  10. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.
  11. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.
  12. Briere, Michael, Flip chip FET device.
  13. Briere,Michael, Flip chip FET device.
  14. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  15. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
  16. Amit P. Marathe ; Pin-Chin Connie Wang ; Christy Mei-Chu Woo, Gradated barrier layer in integrated circuit interconnects.
  17. Murray, Conal E.; Yang, Chih-Chao, Hybrid interconnects and method of forming the same.
  18. Geusic, Joseph E.; Farrar, Paul A.; Bhattacharyya, Arup, Low k interconnect dielectric using surface transformation.
  19. Geusic,Joseph E.; Farrar,Paul A.; Bhattacharyya,Arup, Low k interconnect dielectric using surface transformation.
  20. Vinciarelli,Patrizio; McCauley,Charles I.; Starenas,Paul V., Low loss, high density array interconnection.
  21. Juengling,Werner, Metal to polysilicon contact in oxygen environment.
  22. Duerksen, Kenneth; Vidusek, David A., Method and system for using ion implantation for treating a low-k dielectric film.
  23. Gabric, Zvonimir; Pamler, Werner; Schwarzl, Siegfried, Method for fabricating microstructures and arrangement of microstructures.
  24. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.
  25. Duerksen,Kenneth; Wang,David C.; Soave,Robert J., Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film.
  26. Juengling, Werner, Method of forming a metal to polysilicon contact in oxygen environment.
  27. Juengling, Werner, Method of forming a metal to polysilicon contact in oxygen environment.
  28. Werner Juengling, Method of forming a metal to polysilicon contact in oxygen environment.
  29. Basceri,Cem, Method of forming conductive metal silicides by reaction of metal with silicon.
  30. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
  31. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.
  32. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon.
  33. Grove, Nicole R., Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material.
  34. Sandhu,Gurtej S.; Blalock,Guy T., Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon.
  35. Sandhu,Gurtej S.; Blalock,Guy T., Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon.
  36. Basceri, Cem; Sandhu, Gurtej S.; Manning, H. Montgomery, Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects.
  37. Basceri, Cem; Sandhu, Gurtej S.; Manning, H. Montgomery, Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects.
  38. Basceri,Cem; Sandhu,Gurtej S.; Manning,H. Montgomery, Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects.
  39. Basceri,Cem, Methods of forming conductive material silicides by reaction of metal with silicon.
  40. Derderian, Garo J.; Basceri, Cem, Methods of forming conductive metal silicides by reaction of metal with silicon.
  41. Blalock,Guy T.; Sandhu,Gurtej S.; Daley,Jon P., Methods of forming patterned photoresist layers over semiconductor substrates.
  42. Daley, Jon P., Methods of forming patterned photoresist layers over semiconductor substrates.
  43. Daley, Jon P., Methods of forming patterned photoresist layers over semiconductor substrates.
  44. Daley,Jon P., Methods of forming patterned photoresist layers over semiconductor substrates.
  45. Christy Mei-Chu Woo ; Minh Quoc Tran, Pre-fill CMP and electroplating method for integrated circuits.
  46. Mei Sheng Zhou SG; John Sudijono SG; Subhash Gupta SG; Sudipto Roy SG; Paul Ho SG; Xu Yi SG; Simon Chooi SG; Yakub Aliyu SG, Process without post-etch cleaning-converting polymer and by-products into an inert layer.
  47. Devilbiss,Alan D.; Derbenwick,Gary F., Rectifier utilizing a grounded antenna.
  48. Ueno, Kazuyoshi, Semiconductor device including dual-damascene structure and method for manufacturing the same.
  49. Ahn, Kie Y.; Forbes, Leonard, Semiconductor device with electrically coupled spiral inductors.
  50. Ahn,Kie Y.; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
  51. Ahn,Kie Y; Forbes,Leonard, Semiconductor device with electrically coupled spiral inductors.
  52. Yates,Donald L., Semiconductor processing patterning methods.
  53. Gotkis,Yehiel; Wei,David; Kistler,Rodney, Semiconductor structure implementing low-K dielectric materials and supporting stubs.
  54. Derderian,Garo J.; Basceri,Cem, Semiconductor substrate.
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