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Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/58
  • H01L-029/00
출원번호 US-0845340 (1997-04-25)
발명자 / 주소
  • Havemann Robert H.
  • Jain Manoj K.
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Hoel
인용정보 피인용 횟수 : 44  인용 특허 : 11

초록

An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred embodiments include HSQ (140) as the gap filling low dielectric constant insulator and fluorinated silicon oxid

대표청구항

[ What is claimed is:] [1.]1. An integrated circuit interlevel insulation structure, comprising:(a) a first interconnection level having a plurality of spaced apart conductors havinp, an upper surface and a first insulator region of an electrically insulating material which is highly susceptible to

이 특허에 인용된 특허 (11)

  1. Cohen Stephan A. (Wappingers Falls NY) McGahay Vincent J. (Poughkeepsie NY) Uttecht Ronald R. (Essex Junction VT), Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits.
  2. Kishimoto Koji (Tokyo JPX) Homma Tetsuya (Tokyo JPX), Fabrication process for multilevel interconnections in a semiconductor device.
  3. Cole ; Jr. Herbert S. (Burnt Hills NY) Rose James W. (Guilderland NY), High density interconnect structure including a spacer structure and a gap.
  4. Chiang Chien ; Pan Chuanbin ; Ochoa Vicky M. ; Fang Sychyi ; Fraser David B. ; Sum Joyce C. ; Ray Gary William ; Theil Jeremy A., Interconnect structure with hard mask and low dielectric constant materials.
  5. Kapoor Ashok K. ; Pasch Nicholas F., Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  6. Cole ; Jr. Herbert S. (Scotia NY) Liu Yung S. (Schenectady NY), Multi-sublayer dielectric layers.
  7. Jeng Shin-Puu (Plano TX), Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators.
  8. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  9. Havemann Robert H. (7413 Stillwater Ct. Garland TX 75044), Self-aligned via using low permittivity dielectric.
  10. Sato Junichi,JPX, Semiconductor device making method.
  11. Inoue Kazuhiko,JPX ; Imamura Souichi,JPX ; Ochi Masanori,JPX ; Hosoi Shigehiro,JPX ; Suga Toru,JPX ; Kimura Takashi,JPX, Semiconductor device sealed with molded resin.

이 특허를 인용한 특허 (44)

  1. Maghsoodi, Sina; Motallebi, Shahrokh; Lim, SangHak; Kim, Do-Hyeon, Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods.
  2. Maghsoodi, Sina; Motallebi, Shahrokh; Lim, SangHak; Movassat, Meisam; Kim, Do-Hyeon, Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods.
  3. Chung, Henry, Fabrication of integrated circuits with borderless vias.
  4. Wang, Shi-Qing; Chung, Henry; Lin, James, Integrated circuits with multiple low dielectric-constant inter-metal dielectrics.
  5. Sandhu, Gurtej; Srinivasan, Anand; Iyer, Ravi, Interlevel dielectric structure.
  6. Sandhu, Gurtej; Srinivasan, Anand; Iyer, Ravi, Interlevel dielectric structure and method of forming same.
  7. Wang, Fei; Kai, James K.; Hui, Angela T., Low K dielectic etch in high density plasma etcher.
  8. Lau,Kreisler; Liu,Feng Quan; Apen,Paul; Korolev,Boris; Brouk,Emma; Zherebin,Ruslan; Nalewajek,David; Leung,Roger, Low dielectric constant materials and methods of preparation thereof.
  9. Barth, Karl W.; Kei, Ramona; Kumar, Kaushik A.; Petrarca, Kevin S.; Siddiqui, Shahab, Metal interconnect and IC chip including metal interconnect.
  10. Barth, Karl W.; Kei, Ramona; Kumar, Kaushik A.; Petrarca, Kevin S.; Siddiqui, Shahab, Metal interconnect forming methods and IC chip including metal interconnect.
  11. Guarionex Morales, Method of degassing low k dielectric for metal deposition.
  12. Shigyo, Naoyuki; Yamaguchi, Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.
  13. Shigyo, Naoyuki; Yamaguchi, Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.
  14. Shigyo,Naoyuki; Yamaguchi,Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.
  15. Saito, Masayoshi; Hotta, Katsuhiko; Hirasawa, Masayoshi; Kojima, Masayuki; Uchiyama, Hiroyuki; Maruyama, Hiroyuki; Fukuda, Takuya, Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen.
  16. Saito, Masayoshi; Hotta, Katsuhiko; Hirasawa, Masayoshi; Kojima, Masayuki; Uchiyama, Hiroyuki; Maruyama, Hiroyuki; Fukuda, Takuya, Method of manufacturing semiconductor integrated circuit device having insulatro film formed from liquid containing polymer of silicon, oxygen, and hydrogen.
  17. Tong, Qin-Yi, Method of room temperature covalent bonding.
  18. Okura, Seiji; Oda, Koji; Sawada, Mahito, Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof.
  19. Okura,Seiji; Oda,Koji; Sawada,Mahito, Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof.
  20. Hamada, Koji, Semiconductor device with interlayer film comprising a diffusion prevention layer to keep metal impurities from invading the underlying semiconductor substrate.
  21. Jin, Sin-Hyun; Lee, Jong-Chern, Semiconductor integrated circuit having a multi-chip structure.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  39. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  40. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  41. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  42. Figura, Thomas A.; Donohoe, Kevin G.; Dunbar, Thomas, Use of a plasma source to form a layer during the formation of a semiconductor device.
  43. Figura,Thomas A.; Donohoe,Kevin G.; Dunbar,Thomas, Use of a plasma source to form a layer during the formation of a semiconductor device.
  44. Figura,Thomas A.; Donohoe,Kevin G.; Dunbar,Thomas, Use of a plasma source to form a layer during the formation of a semiconductor device.
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