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Programmable device with an array of programmable cells and interconnection network

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03K-019/177   
미국특허분류(USC) 326/040 ; 326/041 ; 326/038
출원번호 US-0493154 (2000-01-28)
우선권정보 JP0019616 (1999-01-28)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Young & Thompson
인용정보 피인용 횟수 : 53  인용 특허 : 8
초록
▼

The present invention provide a programmable device comprising: an array of plural programmable cells; a first sub-interconnection network comprising a plurality of first interconnections which extend to surround each of the plural programmable cells for transmitting data; and a second sub-interconnection network comprising a plurality of second interconnections which extend to surround each of the plural programmable cells for transmitting control informations, so that each of the plural programmable cells selects one of plural configuable informations ...

대표
청구항
▼

[ What is claimed is:] [1.]1. A programmable device comprising:an array of plural programmable cells connected to an interconnection network, said interconnection network transmitting at least control information to the plural programmable cells, so that each of the plural programmable cells selects one of plural configurable information in accordance with the control information, andeach of the programmable cells comprising at least an internal memory for storing the plural configurable information, said internal memory connected to the interconnection ...

이 특허에 인용된 특허 (8)

  1. Reddy Srinivas T. ; Zaveri Ketan ; Lane Christopher F. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B. ; Mejia Manuel ; Cliff Richard G.. Circuitry and methods for internal interconnection of programmable logic devices. USP2000086107824.
  2. Steele Randy Charles ; Chinnow ; Jr. Duane H.. Field programmable gate array with high speed SRAM based configurable function block configurable as high performance l. USP1998095809281.
  3. Tobias David F.. Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic. USP2000086097988.
  4. Trimberger Stephen M. ; Duong Khue. Multi-buffered configurable logic block output lines in a field programmable gate array. USP1998095815004.
  5. Kelem Steven H. ; Lawman Gary R.. On-chip logic analysis and method for using the same. USP2000086107821.
  6. Nakaya Shogo,JPX. Programmable function block. USP2000106130553.
  7. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; . Programmable logic array integrated circuit devices. USP1998125850152.
  8. Mavis David G.. Tiered routing architecture for field programmable gate arrays. USP2000076094066.

이 특허를 인용한 특허 피인용횟수: 53

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Honary, Hooman; Chen, Inching; Tsui, Ernest T.. Allocation of combined or separate data and control planes. USP2011077975250.
  11. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  12. Kaptanoglu, Sinan; Mendel, David W.. Apparatus and methods for time-multiplex field-programmable gate arrays. USP2014108856711.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  19. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  20. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  21. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  22. Toi,Takao; Awashima,Toru; Miyazawa,Yoshiyuki; Nakamura,Noritsugu; Fujii,Taro; Furuta,Koichiro; Motomura,Masato. Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus. USP2006107120903.
  23. Kami, Hirokazu; Toi, Takao; Awashima, Toru; Anjo, Kenichiro; Furuta, Koichiro; Fujii, Taro; Motomura, Masato. Data processing system for debugging utilizing halts in a parallel device. USP2010017647485.
  24. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  25. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  26. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  27. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  28. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  29. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  30. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  31. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  32. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  33. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  34. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  35. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  36. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  37. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  42. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  43. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  44. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  45. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  46. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  47. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  48. Okamoto,Minoru. Programmable device with structure for storing configuration information. USP2008057378871.
  49. John Morelli ; H. Richard Kendall. Reconfigurable logic for a computer. USP2002086438737.
  50. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  51. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  52. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  53. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.

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