초록 ▼

An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on aft

An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.

대표청구항 ▼

[ We claim:] [1.]1. A programmable output buffer circuit comprising:an input circuit for receiving an input signal, an output enable signal, and for providing first and second data signals each being representative of said input signal;an output terminal for an output signal;a primary driver circuit

[ We claim:] [1.]1. A programmable output buffer circuit comprising:an input circuit for receiving an input signal, an output enable signal, and for providing first and second data signals each being representative of said input signal;an output terminal for an output signal;a primary driver circuit, receiving an output enable signal and said first and second data signals, said primary driver circuit including a first driver circuit coupled to said output terminal for driving, in response to said output enable signal and said first data signal, said output terminal to a first reference voltage, and a second driver circuit coupled to said output terminal for driving, in response to said output enable signal and said second data signal, said output terminal to a second reference voltage; anda boost driver circuit, programmably activated by a selection signal, receiving a boost enable signal and said first and second data signals, said boost enable signal being independent of said output enable signal, and including a first driver circuit coupled to said output terminal for driving, in response to said boost enable signal and said first data signal, said output terminal towards said first reference voltage, and a second driver circuit coupled to said output terminal for driving, in response to said boost enable signal and said second data signal, said output terminal to said second reference voltage.