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Integrated processor and programmable data path chip for reconfigurable computing

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0446762 (2000-05-25)
국제출원번호 PCT/US98/13565 (1998-06-29)
§371/§102 date 20000525 (20000525)
국제공개번호 WO-9900739 (1999-01-07)
발명자 / 주소
  • Wong Dale
  • Phillips Christopher E.
  • Cooke Laurence H.
출원인 / 주소
  • Chameleon Systems, Inc.
대리인 / 주소
    Burns Doane Swecker & Mathis
인용정보 피인용 횟수 : 259  인용 특허 : 15

초록

The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103),

대표청구항

[ What is claimed is:] [1.]1. An integrated circuit, comprising:fine-grain reconfigurable control logic having bit level oriented cells;coarse-grain reconfigurable datapath logic having multiple bit datapath cells; andmemory means coupled to the reconfigurable control logic and the reconfigurable da

이 특허에 인용된 특허 (15)

  1. Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Kuchinski David Christopher ; Knowles Billy Jack ; Nier Richard Edward ; Retter Eric Eugene ; Richardson Robert Reist ; Rolfe, APAP I/O programmable router.
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  175. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  176. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  177. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  178. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  179. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  180. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  181. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
  182. Vorbach, Martin, Methods and devices for treating and/or processing data.
  183. Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.
  184. Tomerlin,Andrew T.; Cafaro,Nicholas G.; Stengel,Robert E., Multiple user reconfigurable CDMA processor.
  185. Sasaki,Paul T.; Menon,Suresh M.; Ghia,Atul V.; Cory,Warren E.; Verma,Hare K.; Freidin,Philip M., Network physical layer with embedded multi-standard CRC generator.
  186. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  187. Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  188. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  189. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  190. Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
  191. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  192. Schulz, Kenneth R; Rapp, John W; Jackson, Larry; Jones, Mark; Cherasaro, Troy, Pipeline accelerator having multiple pipeline units and related computing machine and method.
  193. Schulz,Kenneth R.; Rapp,John W.; Jackson,Larry; Jones,Mark; Cherasaro,Troy, Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method.
  194. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  195. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  196. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
  197. Metzgen, Paul, Pipelined configurable processor.
  198. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  199. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
  200. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  201. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  202. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  203. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  204. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  205. Sato, Tomoyoshi, Program product and data processor.
  206. Callen, Greg S., Programmable ALU.
  207. Simkins, James M.; Young, Steven P.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y., Programmable device with dynamic DSP architecture.
  208. Schultz,David P.; Douglass,Stephen M.; Young,Steven P.; Herron,Nigel G.; Vashi,Mehul R.; Sowards,Jane W., Programmable gate array and embedded circuitry initialization and processing.
  209. Douglass, Stephen M.; Young, Steven P.; Herron, Nigel G.; Vashi, Mehul R.; Sowards, Jane W., Programmable gate array having interconnecting logic to support embedded fixed logic circuitry.
  210. Ansari, Ahmad R., Programmable interactive verification agent.
  211. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
  212. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
  213. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
  214. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with cascading DSP slices.
  215. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with pipelined DSP slices.
  216. Thiele, Matthew J.; Boland, Robert P.; Luthi, Peter O., Reconfigurable compute engine interconnect fabric.
  217. Thiele, Matthew J.; Boland, Robert P.; Luthi, Peter O., Reconfigurable compute engine interconnect fabric.
  218. Rapp, John; Mathur, Chandan; Hellenbach, Scott; Jones, Mark; Capizzi, Joseph A., Reconfigurable computing machine and related systems and methods.
  219. Swoboda, Gary L.; Karthikeyan, Madathil R.; Menon, Amitabh; Matt, David R., Reconfigurable datapath for processor debug functions.
  220. Vorbach, Martin, Reconfigurable elements.
  221. Vorbach, Martin, Reconfigurable elements.
  222. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  223. Vorbach,Martin; M?nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
  224. Tomerlin,Andrew; Cafaro,Nicholas Giovanni; Stengel,Robert E., Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor.
  225. Smith, Stephen J.; Southgate, Timothy J., Reconfigurable programmable logic device computer system.
  226. Vorbach, Martin, Reconfigurable sequencer structure.
  227. Vorbach, Martin, Reconfigurable sequencer structure.
  228. Vorbach, Martin, Reconfigurable sequencer structure.
  229. Vorbach, Martin, Reconfigurable sequencer structure.
  230. Vorbach,Martin, Reconfigurable sequencer structure.
  231. Schulz, Kenneth R.; Hamm, Andrew; Rapp, John, Remote sensor processing system and method.
  232. Vorbach, Martin; Bretz, Daniel, Router.
  233. Vorbach,Martin; Bretz,Daniel, Router.
  234. Vorbach,Martin; M?nch,Robert, Run-time reconfiguration method for programmable units.
  235. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  236. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  237. Gouldey,Brent I.; Fuster,Joel J.; Rapp,John; Jones,Mark, Service layer architecture for memory access system and method.
  238. Metzgen, Paul, Software-to-hardware compiler.
  239. Metzgen,Paul, Software-to-hardware compiler.
  240. Metzgen,Paul, Software-to-hardware compiler.
  241. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
  242. Metzgen,Paul, Software-to-hardware compiler with symbol set inference analysis.
  243. Master,Paul L.; Watson,John, Storage and delivery of device features.
  244. Lai, Andrew W., Structures and methods for testing programmable logic devices having mixed-fabric architectures.
  245. Lai,Andrew W., Structures and methods for testing programmable logic devices having mixed-fabric architectures.
  246. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  247. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  248. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  249. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  250. Ilic, Kosta; Blasig, Dustyn K., Testing a graphical program intended for a programmable hardware element.
  251. Yin, Robert, Testing address lines of a memory controller.
  252. Yin,Robert, Testing address lines of a memory controller.
  253. Burnley, Richard P., Timing performance analysis.
  254. Burnley,Richard P., Timing performance analysis.
  255. Douglass, Stephen M.; Sastry, Prasad L.; Vashi, Mehul R.; Yin, Robert, User configurable memory system having local and global memory blocks.
  256. Ansari, Ahmad R.; Douglass, Stephen M.; Vashi, Mehul R.; Young, Steven P., User configurable on-chip memory system.
  257. Cory, Warren E., Variable data width converter.
  258. Cory, Warren E.; Verma, Hare K.; Ghia, Atul V.; Sasaki, Paul T.; Menon, Suresh M., Variable data width operation in multi-gigabit transceivers on a programmable logic device.
  259. Cory, Warren E.; Verma, Hare K.; Ghia, Atul V.; Sasaki, Paul T.; Menon, Suresh M., Variable data width operation in multi-gigabit transceivers on a programmable logic device.
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