초록 ▼

Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors hav

Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The threshold voltages are determined by extrapolation from the (high) gate to source voltage. Each of the N-channel transistors is paired with a corresponding P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage equal to the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage.

대표청구항 ▼

[ What is claimed is:] [1.]1. An optimized digital system comprising:a plurality of metal oxide field effect transistors each of said transistors having a drain, a source, a gate, a channel current, and a gate voltage, said channel current and said gate voltage related by an IV plot,said transistors

[ What is claimed is:] [1.]1. An optimized digital system comprising:a plurality of metal oxide field effect transistors each of said transistors having a drain, a source, a gate, a channel current, and a gate voltage, said channel current and said gate voltage related by an IV plot,said transistors forming complementary symmetry pairs, each of said transistors having a high side conduction threshold voltage,said threshold voltage set by said channel current flowing between said drain and said source,said channel current at an operating point in a digital circuit where said current is approaching saturation,said high side conduction threshold voltage computed from the extension of a slope of said channel current at said operating point in said IV plot to intersect said gate voltage at a point on said IV plot where said channel current is zero; anda pre-computed voltage connected across said plurality of metal oxide field effect transistors,said precomputed voltage optimized for minimum time delay and minimum power dissipation across said plurality of metal oxide field effect transistors,said pre-computed voltage nominally equal to the sum of two of said high side conduction threshold voltages, said pre-computed voltage other than nominal 5 volts, 3.3 volts, 1.8 volts, 1.6 volts and 0.9 volts.