$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of defining copper seed layer for selective electroless plating processing

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0225175 (1999-01-04)
발명자 / 주소
  • Yu Allen S.
  • Steffan Paul J.
  • Scholer Thomas C.
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Nelson
인용정보 피인용 횟수 : 30  인용 특허 : 10

초록

A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed

대표청구항

[ What is claimed is:] [1.]1. A method of manufacturing a semiconductor wafer, the method comprising:forming a partially completed semiconductor wafer having at least one trench formed in a layer of interlayer dielectric;forming a conformal barrier layer on a surface of the interlayer dielectric inc

이 특허에 인용된 특허 (10)

  1. Liu Chung-Shi,TWX ; Chang Chung-Long,TWX ; Yu Chen-Hua,TWX, Copper chemical-mechanical-polishing (CMP) dishing.
  2. Allen Gregory Lee (Vancouver WA), Implantation of nucleating species for selective metallization and products thereof.
  3. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  4. Chan Lap ; Ng Hou Tee,SGX, Method for planarized interconnect vias using electroless plating and CMP.
  5. Uzoh Cyprian Emeka ; Greco Stephen Edward, Method to selectively fill recesses with conductive metal.
  6. Schinella Richard (Saratoga CA) Sanganeria Mahesh K. (Sunnyvale CA), Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate.
  7. Schinella Richard ; Sanganeria Mahesh K., Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate.
  8. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  9. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  10. Nogami Takeshi ; Dubin Valery M., Via with barrier layer for impeding diffusion of conductive material from via into insulator.

이 특허를 인용한 특허 (30)

  1. Uzoh,Cyprian Emeka; Talieh,Homayoun; Basol,Bulent, Chip interconnect and packaging deposition methods and structures.
  2. Kung, Chen-Yueh, Circuit substrate.
  3. Kitch, Vassili, Fabrication of copper-containing region such as electrical interconnect.
  4. Kitch,Vassili, Fabrication technique using sputter etch and vacuum transfer.
  5. Lee,Sang Gi; Lee,Chang Eun, Method for fabricating transistor of semiconductor device.
  6. John A. Iacoponi ; Paul R. Besser ; Frederick N. Hause ; Frank Mauersberger DE; Errol Todd Ryan ; William S. Brennan ; Peter J. Beckage, Method for forming copper interconnects.
  7. Cho, Jae-Choon; Hong, Myeong-Ho; Ra, Senug-Hyun; Lee, Hyuk-Soo; Kwak, Jeong-Bok; Lee, Jung-Woo; Lee, Choon-Keun; Lee, Sang-Moon, Method for manufacturing printed circuit board using imprinting.
  8. Lin, Bih-Tiao, Method of fabricating copper damascene.
  9. Gilton, Terry L.; Chopra, Dinesh, Method of forming a metal seed layer for subsequent plating.
  10. Terry L. Gilton ; Dinesh Chopra, Method of forming a metal seed layer for subsequent plating.
  11. Egitto, Frank D.; Foster, Elizabeth; Galasco, Raymond T.; Markovich, Voya R.; Nguyen, Manh-Quan Tam, Method of forming filled blind vias.
  12. Matsui, Yoshitaka; Kodera, Masako, Method of manufacturing a semiconductor device using a wet process.
  13. Matsui, Yoshitaka; Kodera, Masako, Method of manufacturing a semiconductor device using a wet process.
  14. Yamaguchi, Masahiro, Method of manufacturing semiconductor device.
  15. Woo, Christy Mei-Chu; Wang, Pin-Chin Connie, Method of promoting void free copper interconnects.
  16. LaPlante, Mark J.; Casey, Jon A.; Wassick, Thomas A.; Long, David C.; Semkow, Krystyna W.; Spencer, Patrick E.; Rita, Robert A.; Indyk, Richard F.; Wiley, Kathleen M.; Sundlof, Brian R.; Balz, James;, Method of selective plating on a substrate.
  17. Cohen,Adam L.; Smalley,Dennis R., Methods for electrochemically fabricating multi-layer structures including regions incorporating maskless, patterned, multiple layer thickness depositions of selected materials.
  18. Smalley, Dennis R., Methods of and apparatus for electrochemically fabricating structures via interlaced layers or via selective etching and filling of voids.
  19. Smalley, Dennis R., Methods of and apparatus for electrochemically fabricating structures via interlaced layers or via selective etching and filling of voids.
  20. Smalley, Dennis R., Methods of and apparatus for electrochemically fabricating structures via interlaced layers or via selective etching and filling of voids.
  21. Catabay, Wilbur G.; Wang, Zhihai; Li, Ping, Multi-step process for forming a barrier film for use in copper layer formation.
  22. Catabay,Wilbur G.; Wang,Zhihai; Li,Ping, Multi-step process for forming a barrier film for use in copper layer formation.
  23. Catabay,Wilbur G.; Wang,Zhihai; Li,Ping, Multi-step process for forming a barrier film for use in copper layer formation.
  24. Mayer, Steven T.; Drewery, John Stephen; Webb, Eric G., Photoresist-free metal deposition.
  25. Basol, Bulent M., Plating methods for low aspect ratio cavities.
  26. Lubomirsky, Dmitry; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Kovarsky, Nicolay Y.; Wijekoon, Kapila, Process for electroless copper deposition.
  27. Cotte, John Michael; McCullough, Kenneth John; Moreau, Wayne Martin; Pope, Keith R.; Simons, John P.; Taft, Charles J.; Volant, Richard P., Process of providing a semiconductor device with electrical interconnection capability.
  28. Morgan, Paul A.; Sinha, Nishant, Selective metal deposition over dielectric layers.
  29. Morgan, Paul A; Sinha, Nishant, Selective metal deposition over dielectric layers.
  30. Lim, Yeow Kheng; See, Alex; Lee, Tae Jong; Vigar, David; Hsia, Liang Choo; Pey, Kin Leong, Slot designs in wide metal lines.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트