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Method and apparatus for forming improved metal interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0126890 (1998-07-31)
발명자 / 주소
  • Hashim Imran
  • Chiang Tony
  • Chin Barry
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Dugan
인용정보 피인용 횟수 : 84  인용 특허 : 11

초록

Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and f

대표청구항

[ The invention claimed is:] [1.]1. A method of forming a contact between a first metal layer and a second metal layer comprising:providing a first metal layer;providing a first dielectric layer disposed on the first metal layer, the first dielectric layer being one in which atoms of the first metal

이 특허에 인용된 특허 (11)

  1. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  2. Joshi Rajiv Vasant ; Tejwani Manu Jamnadas ; Srikrishnan Kris Venkatraman, High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap.
  3. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  4. Yamamoto Hiroshi (Chiba JPX) Takeyasu Nobuyuki (Chiba JPX) Ohta Tomohiro (Urayasu JPX), Method of forming multilayered wiring structure in semiconductor device.
  5. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  6. Inohara Masahiro,JPX ; Anand Minakshisundaran Balasubramanian,JPX ; Matsuno Tadashi,JPX, Method of manufacturing semiconductor device having multi-layer wiring structure with diffusion preventing film.
  7. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  8. Lou Chine-Gie,TWX, Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits.
  9. Agarwala Birendra N. (Hopewell Junction NY), Process of making pad structure for solder ball limiting metallurgy having reduced edge stress.
  10. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  11. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.

이 특허를 인용한 특허 (84)

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