Device and method for generating clock signals from a single reference frequency signal and for synchronizing data signals with a generated clock
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-025/36
H04L-025/40
H04L-007/00
출원번호
US-0322282
(1999-05-28)
발명자
/ 주소
Nguyen Tien Q.
McDonough John G.
Chen David
Tran Howard Thien
출원인 / 주소
VLSI Technology, Inc.
대리인 / 주소
Hernandez
인용정보
피인용 횟수 :
15인용 특허 :
15
초록▼
An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiv
An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S). When in a secondary power savings mode, the pulse swallower produces an output signal having a frequency of chiprate which is used to maintain CDMA network time, permitting the analog transceiver to be powered down during the secondary mode. In another embodiment of the invention, the external clock signal from the analog transceiver having a frequency of chiprate(S) is multiplied by (n) to produce the primary digital transceiver clock signal.
대표청구항▼
[ What is claimed is:] [1.]1. An integrated circuit device for generating a plurality of internal clock signals and synchronizing data signals with one of the generated clock signals, comprising:a FIFO having a data bus output, a data bus input for coupling to an output providing the data signals, a
[ What is claimed is:] [1.]1. An integrated circuit device for generating a plurality of internal clock signals and synchronizing data signals with one of the generated clock signals, comprising:a FIFO having a data bus output, a data bus input for coupling to an output providing the data signals, an external clock input for coupling to an output providing a first external clock signal for clocking the data signals into the FIFO at a frequency of chiprate(S), and an output clock input coupled to an output providing a FIFO output clock signal for clocking the data signals out of the FIFO at a frequency of chiprate(S), the external clock signal being asynchronous with the FIFO output clock signal;a clock generator, comprising:a PLL having an output, and an input for coupling to an output providing a second external clock signal, the PLL multiplying the frequency of the second external clock signal by p to produce a primary digital transceiver clock signal at the output of the PLL having a frequency of chiprate(S)(n), wherein chiprate, S, and n are numerical values;a first clock divider having an input and an output, the input of the first clock divider being coupled to the output of the PLL, the output of the first clock divider being coupled to the output clock input of the FIFO, the first clock divider producing the FIFO output clock signal at the output of the first clock divider;a pulse swallower having an output, and an input for coupling to an output providing a reference frequency signal from a reference frequency source, the pulse swallower producing a secondary master clock signal at the output of the pulse swallower having a frequency of chiprate(z), wherein z is a numerical value; anda first multiplexer having a first input, a second input, a control input, and an output, the first input of the multiplexer being coupled to the output of the pulse swallower, the second input of the multiplexer being coupled to the output of the PLL; anda controller having a control output coupled to the control input of the first multiplexer, the controller producing a control signal at the control output for selectively providing either the primary digital transceiver clock signal from the output of the PLL or the secondary master clock signal from the output of the pulse swallower at the output of the first multiplexer.
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