초록 ▼

The present invention provides a system for learning from and responding to regularly arriving information at once by quickly combining prior information with concurrent trial information to produce useful learned information. A parallel embodiment of the system performs can perform updating operati

The present invention provides a system for learning from and responding to regularly arriving information at once by quickly combining prior information with concurrent trial information to produce useful learned information. A parallel embodiment of the system performs can perform updating operations for memory elements of matrix through the coordinated use of parallel feature processors and a joint access memory, which contains weighted values and provision for connecting feature processors pairwise. The parallel version also performs feature function monitoring, interpretation and refinement operations promptly and in concert with concurrent operation. A non-parallel embodiment of the system uses a single processor to perform the above operations however, more slowly than the parallel embodiment, yet faster than available alternatives.

대표청구항 ▼

[ I claim:] [1.]1. A parallel processing system for computing output values from input values received during a time trial, comprising:a plurality of processing units, each of said processing units operative to receive, during a time trial and in parallel, individual input values from an input vecto

[ I claim:] [1.]1. A parallel processing system for computing output values from input values received during a time trial, comprising:a plurality of processing units, each of said processing units operative to receive, during a time trial and in parallel, individual input values from an input vector, said processing units comprising analogs components for computing arithmetic operations of said system;a plurality of interconnected conductors, operative to connect each of said processing units to every other processing unit of said system and operative to transfer weighted values among said processors;a plurality of switching junctions located along said interconnected conductors, said switching junctions being operable for uniquely pairing each of said processors to every other processor of said system; andeach of said processing units operative to provide, during said time trial, an expected output value based on said weighted values and each of said processing units operative to update, during said time trial, said weighted values based on said input values.