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Method of electroless ag layer formation for cu interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-015/20
  • H01L-023/52
출원번호 US-0592164 (2000-06-13)
발명자 / 주소
  • Lopatin Sergey
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Winters
인용정보 피인용 횟수 : 30  인용 특허 : 6

초록 ▼

A dielectric layer has an opening which communicates with a metal line therebeneath. A layer of silver is deposited over the structure and into the opening, and copper is deposited by electroplating in the opening. An additional silver layer is the deposited, and an anneal step is undertaken so that

대표청구항 ▼

[ What is claimed is:] [7.]7. a semiconductor structure comprising:a dielectric layer having an opening therein;a layer comprising palladium in the opening and on and in contact with the dielectric layer;a layer comprising silver in the opening on the layer comprising palladium; anda conductor compr

이 특허에 인용된 특허 (6)

  1. Nogami Takeshi ; Pramanick Shekhar ; Brown Dirk, Copper interconnect methodology for enhanced electromigration resistance.
    상세보기
  2. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
    상세보기
  3. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
    상세보기
  4. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
    상세보기
  5. Cohen Uri, Seed layers for interconnects and methods for fabricating such seed layers.
    상세보기
  6. Chan Tsiu C. ; Chiu Anthony M. ; Smith Gregory C., Silver metallization by damascene method.
    상세보기

이 특허를 인용한 특허 (30)

  1. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
    상세보기
  2. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
    상세보기
  3. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
    상세보기
  4. Agarwal, Vishnu Kumar, Encapsulated conductive pillar.
    상세보기
  5. Gurumurthy, Charan; Salama, Islam; Jomaa, Houssam; Tanikella, Ravi, Integrated circuit and process for fabricating thereof.
    상세보기
  6. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  7. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  8. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  9. Kim, Jae-Jeong; Kim, Soo-Kil; Kim, Yong-Shik, Low resistivity copper conductor line, liquid crystal display device having the same and method for forming the same.
    상세보기
  10. Lopatin,Sergey; Shanmugasundram,Arulkumar; Lubomirsky,Dmitry; Pancham,Ian A., Method for forming CoWRe alloys by electroless deposition.
    상세보기
  11. Dubin,Valery M.; Chebiam,Ramanan V., Method for making a semiconductor device having increased conductive material reliability.
    상세보기
  12. Dubin,Valery M.; Chebiam,Ramanan V., Method for making a semiconductor device having increased conductive material reliability.
    상세보기
  13. Lopatin, Sergey D.; Galewski, Carl; Nogami, Takeshi T. N., Method of copper interconnect formation using atomic layer copper deposition and a device thereby formed.
    상세보기
  14. Agarwal, Vishnu Kumar, Method of forming an encapsulated conductive pillar.
    상세보기
  15. Naoaki Ogure JP; Hiroaki Inoue JP, Method of forming embedded copper interconnections and embedded copper interconnection structure.
    상세보기
  16. Ogure, Naoaki; Inoue, Hiroaki, Method of forming embedded copper interconnections and embedded copper interconnection structure.
    상세보기
  17. Kesari, Susrut; Lamanna, William M.; Parent, Michael J.; Zazzera, Lawrence A., Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor.
    상세보기
  18. Zazzera, Lawrence A.; Parent, Michael J.; Lamanna, William M.; Kesari, Susrut, Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor.
    상세보기
  19. Inoue,Hiroaki; Wang,Xinming; Matsumoto,Moriji; Kanayama,Makoto, Plating solution, semiconductor device and method for manufacturing the same.
    상세보기
  20. Boyd,Steven D.; Kesari,Susrut; Lamanna,William M.; Parent,Michael J.; Zazzera,Lawrence A.; Zhang,Haiyan, Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor.
    상세보기
  21. Lopatin,Sergey; Shanmugasundram,Arulkumar; Emami,Ramin; Fang,Hongbin, Pretreatment for electroless deposition.
    상세보기
  22. Lubomirsky, Dmitry; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Kovarsky, Nicolay Y.; Wijekoon, Kapila, Process for electroless copper deposition.
    상세보기
  23. Ueno,Kazuyoshi, Semiconductor device.
    상세보기
  24. Ueno,Kazuyoshi, Semiconductor device and manufacturing process therefor as well as plating solution.
    상세보기
  25. Ueno, Kazuyoshi, Semiconductor device with improved stress migration resistance and manufacturing process therefor.
    상세보기
  26. Inoue,Hiroaki; Kimura,Norio; Wang,Xinming; Matsumoto,Moriji; Kanayama,Makoto, Semiconductor device, method for manufacturing the same, and plating solution.
    상세보기
  27. Inoue,Hiroaki; Kimura,Norio; Wang,Xinming; Matsumoto,Moriji; Kanayama,Makoto, Semiconductor device, method for manufacturing the same, and plating solution.
    상세보기
  28. Lopatin,Sergey D.; Shanmugasundrum,Arulkumar; Shacham Diamand,Yosef, Silver under-layers for electroless cobalt alloys.
    상세보기
  29. Krishnashree Achuthan ; Sergey Lopatin, Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure.
    상세보기
  30. Gallo, Antonio R.; Gopalan, Chakravarthy; Ma, Yi, Variable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same.
    상세보기

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