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Multistack 3-dimensional high density semiconductor device and method for fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-027/01
  • H01L-027/12
  • H01L-031/039.2
출원번호 US-0477249 (2000-01-03)
발명자 / 주소
  • Ma William Hsioh-Lien
  • Schepis Dominic Joseph
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Connolly Bove Lodge & HutzAbate
인용정보 피인용 횟수 : 59  인용 특허 : 14

초록 ▼

A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and

대표청구항 ▼

[ What is claimed is:] [1.]1. A multistack 3-D semiconductor single wafer structure comprising:a first level structure comprising a first semiconductor substrate and first active devices; anda second level structure comprising a SOI semiconductor structure bonded to the first level structure and fur

이 특허에 인용된 특허 (14)

  1. Spangler Leland J. (1974 Traver Rd. ; Apt. No. 208 Ann Arbor MI 48105) Wise Kensall D. (3670 Charter Pl. Ann Arbor MI 48105), Fully integrated single-crystal silicon-on-insulator process, sensors and circuits.
    상세보기
  2. Zavracky Paul M. (Norwood MA) Zavracky Matthew (Attleboro MA) Vu Duy-Phach (Taunton MA) Dingle Brenda (Mansfield MA), Method for forming three dimensional processor using transferred thin film circuits.
    상세보기
  3. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform.
    상세보기
  4. Park Kyucharn (Kyungki-do KRX) Lee Yeseung (Seoul KRX) Ban Cheonsu (Seoul KRX) Lee Kyungwook (Kyungki-do KRX), Method for making a dynamic random access memory using silicon-on-insulator techniques.
    상세보기
  5. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Method for the production of a three-dimensional circuit arrangement.
    상세보기
  6. Leedy Glenn Joseph (Montecito CA), Method of making a stacked 3D integrated circuit structure.
    상세보기
  7. Harada Masana (Itami JPX), Method of producing a semiconductor device.
    상세보기
  8. Liu Yowjuang William, Multilayer floating gate field effect transistor structure for use in integrated circuit devices.
    상세보기
  9. Sun Shih-Wei (Austin TX), Process for forming semiconductor-on-insulator device.
    상세보기
  10. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
    상세보기
  11. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
    상세보기
  12. Kikuchi Hiroaki,JPX ; Arai Kenichi,JPX, Semiconductor substrate with SOI structure.
    상세보기
  13. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
    상세보기
  14. Matsushita Takeshi,JPX, Three-dimensional integrated circuit device and its manufacturing method.
    상세보기

이 특허를 인용한 특허 (59)

  1. Lukes,Eric John; Phan,Nghia Van, Array split across three-dimensional interconnected chips.
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  2. Chan, Philip Ching Ho; Chan, Man Sun; Wu, Xusheng; Zhang, Shengdong, Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits.
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  3. Lee, Thomas H., Dense arrays and charge storage devices.
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  4. Lee, Thomas H., Dense arrays and charge storage devices.
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  5. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Johnson, Mark G.; Farmwald, Paul Michael; Kouznetzov, Igor G., Dense arrays and charge storage devices.
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  6. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Kouznetsov, Igor G.; Johnson, Mark G.; Farmwald, Paul Michael, Dense arrays and charge storage devices.
    상세보기
  7. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Kouznetsov, Igor G.; Johnson, Mark G.; Farmwald, Paul Michael, Dense arrays and charge storage devices.
    상세보기
  8. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Kouznetzov, Igor G.; Johnson, Mark G.; Farmwald, Paul Michael, Dense arrays and charge storage devices.
    상세보기
  9. Lee,Thomas H.; Subramanian,Vivek; Cleeves,James M.; Walker,Andrew J.; Petti,Christopher; Kouznetzov,Igor G.; Johnson,Mark G.; Farmwald,Paul M.; Herner,Brad, Dense arrays and charge storage devices.
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  10. Zhang, Yanli; Makala, Raghuveer S.; Alsmeier, Johann, Enhanced channel mobility three-dimensional memory structure and method of making thereof.
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  11. Patel, Kedar; Ilkbahar, Alper; Scheuerlein, Roy; Walker, Andrew J., High density 3D rail stack arrays.
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  12. Patel, Kedar; Ilkbahar, Alper; Scheuerlein, Roy; Walker, Andrew J., High density 3d rail stack arrays and method of making.
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  13. Johnson, Mark G.; Lee, Thomas H.; Cleeves, James M., Integrated circuit incorporating decoders disposed beneath memory arrays.
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  14. Johnson,Mark G.; Lee,Thomas H.; Cleeves,James M., Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement.
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  15. Gonzalez, Fernando; Zahurak, John K., Localized biasing for silicon on insulator structures.
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  16. Gonzalez, Fernando; Zahurak, John K., Localized biasing for silicon on insulator structures.
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  17. Gonzalez, Fernando; Zahurak, John K., Localized biasing for silicon on insulator structures.
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  18. Gonzalez, Fernando; Zahurak, John K., Localized biasing for silicon on insulator structures.
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  19. Chhor,Khushrav S.; Lee,Tae Hee, Memory card with enhanced testability and methods of making and using the same.
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  20. Johnson,Mark G., Memory device and method for simultaneously programming and/or reading memory cells on different levels.
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  21. Verma, Vani; Chhor, Khushrav S., Memory module having interconnected and stacked integrated circuits.
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  22. Verma,Vani; Chhor,Khushrav S., Memory module having interconnected and stacked integrated circuits.
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  23. Verma,Vani; Chhor,Khushrav S., Memory module having interconnected and stacked integrated circuits.
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  24. Campbell, John E.; Devine, William T.; Srikrishnan, Kris V., Method and structure for buried circuits and devices.
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  25. Campbell,John E.; Devine,William T.; Srikrishnan,Kris V., Method and structure for buried circuits and devices.
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  26. Campbell,John E.; Devine,William T.; Srikrishnan,Kris V., Method and structure for buried circuits and devices.
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  27. Campbell,John E.; Devine,William T.; Srikrishnan,Kris V., Method and structure for buried circuits and devices.
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  28. Gormley, Colin Stephen; Brown, Stephen Alan; Blackstone, Scott Carlton, Method for forming a semiconductor device and a semiconductor device formed by the method.
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  29. William Hsioh-Lien Ma ; Dominic Joseph Schepis, Method of fabricating a multistack 3-dimensional high density semiconductor device.
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  30. Chhor, Khushrav S.; Moresco, Larry L., Molded memory module and method of making the module absent a substrate support.
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  31. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Walker, Andrew J.; Petti, Christopher J.; Kouznetzov, Igor G.; Johnson, Mark G.; Farmwald, Paul Michael; Herner, Brad, Monolithic three dimensional array of charge storage devices containing a planarized surface.
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  32. Walker, Andrew J.; Johnson, Mark G.; Knall, N. Johan; Kouznetsov, Igor G.; Petti, Christopher J., Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication.
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  33. Johnson, Mark G.; Lee, Thomas H.; Subramanian, Vivek; Farmwald, Paul Michael; Cleeves, James M., Pillar-shaped nonvolatile memory and method of fabrication.
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  34. Lee,Thomas H.; Walker,Andrew J.; Petti,Christopher J.; Kouznetzov,Igor G., Rail stack array of charge storage devices and method of making same.
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  35. Herner, S. Brad, Silicide-silicon oxide-semiconductor antifuse device and method of making.
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  36. Herner, S. Brad, Silicide-silicon oxide-semiconductor antifuse device and method of making.
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  37. Herner,S. Brad, Silicide-silicon oxide-semiconductor antifuse device and method of making.
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  38. Johnson, Mark G.; Knall, N. Johan; Herner, S. Brad, Silicon nitride antifuse for use in diode-antifuse memory arrays.
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  39. Walker, Andrew J.; Petti, Christopher, TFT mask ROM and method for making same.
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  40. Walker, Andrew J.; Petti, Christopher, TFT mask ROM and method for making same.
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  41. Walker,Andrew J.; Petti,Christopher, TFT mask ROM and method for making same.
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  42. Walker, Andrew J., Thin film transistors with vertically offset drain regions.
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  43. Pachamuthu, Jayavel; Rabkin, Peter; Xia, Jilin; Petti, Christopher, Three dimensional memory device containing aluminum source contact via structure and method of making thereof.
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  44. Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Johnson, Mark G.; Farmwald, Paul M.; Kouznetsov, Igor G., Three terminal nonvolatile memory device with vertical gated diode.
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  45. Johnson, Mark G.; Lee, Thomas H.; Subramanian, Vivek; Farmwald, Paul Michael; Cleeves, James M., Three-dimensional nonvolatile memory and method of fabrication.
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  46. Johnson, Mark G., Three-dimensional, mask-programmed read only memory.
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  47. Kouznetsov, Igor G.; Walker, Andrew J., Two mask floating gate EEPROM and method of making.
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  48. Kouznetsov, Igor G.; Walker, Andrew J., Two mask floating gate EEPROM and method of making.
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  49. Cleeves,James M.; Subramanian,Vivek, Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  50. Johnson, Mark G.; Lee, Thomas H.; Subramanian, Vivek; Farmwald, Paul Michael, Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  51. Johnson, Mark G.; Lee, Thomas H.; Subramanian, Vivek; Farmwald, Paul Michael; Cleeves, James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  52. Johnson, Mark G.; Lee, Thomas H.; Subramanian, Vivek; Farmwald, Paul Michael; Cleeves, James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  53. Mark G. Johnson ; Thomas H. Lee ; Vivek Subramanian ; Paul Michael Farmwald ; James M. Cleeves, Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  54. Subramanian, Vivek; Cleeves, James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  55. Subramanian,Vivek; Cleeves,James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  56. Subramanian,Vivek; Cleeves,James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  57. Subramanian,Vivek; Cleeves,James M., Vertically stacked field programmable nonvolatile memory and method of fabrication.
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  58. Johnson, Mark G., Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication.
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  59. Johnson, Mark G., Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication.
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