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Process for forming an electrical device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0602099 (2000-06-26)
발명자 / 주소
  • Flynn Todd M.
  • Argento Christopher W.
  • Larsen Larry J.
출원인 / 주소
  • Motorola, Inc.
대리인 / 주소
    Meyer
인용정보 피인용 횟수 : 63  인용 특허 : 4

초록

The present invention includes a process for forming an electrical device. In one embodiment, the process includes applying a solid patternable film over a substrate and forming a conductive material over the substrate while the solid patternable film overlies the substrate, wherein the conductive m

대표청구항

[ What is claimed is:] [1.]1. A process for forming an electrical device comprising:applying a solid patternable film over a substrate wherein the solid patternable film is further characterized as a tape film; andforming a first conductive material over the substrate while the solid patternable fil

이 특허에 인용된 특허 (4)

  1. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.
  2. Crafts Douglas E. (San Jose CA) Murali Venkatesan (San Jose CA) Lee Caroline S. (Fresh Meadows NY), Process for single mask C4 solder bump fabrication.
  3. Dass M. Lawrence A. ; Roggel Amir ; Seshan Krishna, Process for sort testing C4 bumped wafers.
  4. Eichelberger Charles William, Single chip modules, repairable multichip modules, and methods of fabrication thereof.

이 특허를 인용한 특허 (63)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  3. Wang, Qifeng, Chip packaging structures.
  4. Wang, Qifeng, Chip packaging structures and treatment methods thereof.
  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  8. Oh,Jae Young; Kim,Soo Pool, Etching tape and method of fabricating array substrate for liquid crystal display using the same.
  9. Drexl, Stefan; Goebel, Thomas; Helneder, Johann; Hommel, Martina; Klein, Wolfgang; Kôrner, Heinrich; Mitchell, Andrea; Schwerd, Markus; Seck, Martin, Integrated connection arrangements.
  10. Farrar,Paul A., Interconnect alloys and methods and apparatus using same.
  11. Farrar,Paul A., Interconnect alloys and methods and apparatus using same.
  12. Mis, J. Daniel; Rinne, Glenn A., Lead free alloy bump structure and fabrication method.
  13. Adachi,Hiroki; Nishi,Kazuo; Yonezawa,Masato; Isobe,Yukihiro; Shinohara,Hisato, Method for manufacturing semiconductor device.
  14. Ghosh, Amalkumar P.; Liu, Yachin; Ji, Hua Xia, Method of clearing electrical contact pads in thin film sealed OLED devices.
  15. Robl, Werner; Goebel, Thomas; Brintzinger, Axel Christoph; Friese, Gerald, Method of eliminating back-end rerouting in ball grid array packaging.
  16. Okajima, Takehiko; Ikeya, Masahisa, Method of fabricating a semiconductor device with a gold conductive layer and organic insulating layer.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  19. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  20. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  21. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  22. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  23. Chen, Yen-Ming; Lin, Chia-Fu; Hsu, Shun-Liang; Ching, Kai-Ming; Lee, Hsin-Hui; Su, Chao-Yuan; Chen, Li-Chih, Method to improve bump reliability for flip chip device.
  24. Farrar, Paul A.; Eldridge, Jerome, Micro C-4 semiconductor die.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  26. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Pad cushion structure and method of fabrication for Pb-free C4 integrated circuit chip joining.
  27. Chen, Hsien-Wei, Passivation scheme.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  29. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  31. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  32. Ishihara,Shosaku; Ikeda,Osamu; Kajiwara,Ryouichi; Hiramitsu,Shinji; Matsuyoshi,Satoshi, Semiconductor device.
  33. Sahara, Ryuichi; Watase, Kazumi; Kumakawa, Takahiro; Kainoh, Kazuyuki; Shimoishizaka, Nozomi, Semiconductor device and method for producing the same.
  34. Yoo,Cheol Joon, Semiconductor device and method of packaging the same.
  35. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  36. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  37. Daubenspeck, Timothy H.; Fortier, Paul; Gambino, Jeffrey P.; Muzzy, Christopher D.; Questad, David L.; Sauter, Wolfgang; Sullivan, Timothy D., Structures and methods to improve lead-free C4 interconnect reliability.
  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  48. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  49. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  50. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  51. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  53. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  54. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  55. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  56. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  61. Fang, Jen-Kuang, Wafer level chip-scale package.
  62. Chou, Chiu-Ming; Lin, Shih-Hsiung; Lin, Mou-Shiung; Lo, Hsin-Jung, Wire bonding method for preventing polymer cracking.
  63. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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