초록 ▼

The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdop

The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

대표청구항 ▼

[ What is claimed is:] [1.]1. A integrated circuit resistor fabricated in a substrate having a surface, the resistor comprising:a contiguous first conductivity type region formed in the substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant d

[ What is claimed is:] [1.]1. A integrated circuit resistor fabricated in a substrate having a surface, the resistor comprising:a contiguous first conductivity type region formed in the substrate, wherein the first conductivity type region has a dopant depth that is approximately equal to a dopant depth of a first conductivity type transistor source/drain region formed elsewhere in the substrate and also has a length L.sub.1, a width W.sub.1, and a depth D.sub.1, and in which L.sub.1 and W.sub.1 define an area substantially parallel to the surface of the semiconductor substrate, and D.sub.1 extends substantially orthogonally to each of L.sub.1 and W.sub.1 into the substrate;at least two electrical contacts to the first conductivity type region for allowing current flow between the contacts through the first conductivity type region; andat least one second conductivity type region formed in the substrate such that the second conductivity type region at least partially intersects the first conductivity type region for increasing resistance to the current flow between the contacts, wherein the second conductivity type region has a dopant depth that is approximately equal to a dopant depth of a second conductivity type transistor source/drain region formed elsewhere in the substrate and also has a length L.sub.2, a width W.sub.2, and a depth D.sub.2, and in which L.sub.2 and W.sub.2 define an area substantially parallel the surface of the semiconductor substrate, and D.sub.2 extends substantially orthogonally to each of L.sub.2 and W.sub.2 into the substrate and is approximately equal to the depth D.sub.1 ;L.sub.1 and L.sub.2 are substantially parallel to each other; andthe area defined by L.sub.2 and W.sub.2 at least partially intersects the area defined by L.sub.1 and W.sub.1.