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Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/34
출원번호 US-0173257 (1998-10-14)
발명자 / 주소
  • Mohamed Moataz A.
  • Spence John R.
  • Malich Kenneth W.
출원인 / 주소
  • Conexant Systems, Inc.
대리인 / 주소
    Snell & Wilmer LLP
인용정보 피인용 횟수 : 77  인용 특허 : 15

초록

The present invention provides an efficient method of forwarding and sharing information between functional units and register files in an effort to execute instructions. A digital signal processor includes a plurality of register blocks for storing data operands coupled to a plurality of data path

대표청구항

[ What is claimed is:] [1.]1. A digital signal processor for use in executing a plurality of instructions contained in an instruction packet, said processor comprising:a plurality of register blocks, each containing operands;a plurality of data path units, wherein each of said data path units compri

이 특허에 인용된 특허 (15)

  1. Ahsan Agha Y. (San Jose CA) Rockwood Christopher B. (Sunnyvale CA), Circuit for preservation of sign information in operations for comparison of the absolute value of operands.
  2. Date Atsushi,JPX ; Hamaguchi Kazumasa,JPX ; Kosugi Masato,JPX ; Fukui Toshiyuki,JPX, Higher-speed parallel processing.
  3. Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
  4. Saito Masahiko,JPX ; Kurosawa Kenichi,JPX ; Kobayashi Yoshiki,JPX ; Bandoh Tadaaki,JPX ; Iwamura Masahiro,JPX ; Hotta Takashi,JPX ; Nakatsuka Yasuhiro,JPX ; Tanaka Shigeya,JPX ; Takemoto Takeshi,JPX, Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memo.
  5. Ebcioglu Mahmut K. (Somers NY) Luick David A. (Rochester MN) Moreno Jaime H. (Hartsdale NY) Silberman Gabriel M. (Millwood NY) Winterfield Philip B. (Rochester MN), Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor.
  6. Baxter Michael Alan, Minimal instruction set computer architecture and multiple instruction issue method.
  7. Harrison ; Jr. Earnest R. (Severna Park MD), Multi-processor computer system bus architecture.
  8. Luick David Arnold (Rochester MN), Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n.
  9. Park Heonchul ; Song Seungyoon P., Opportunistic operand forwarding to minimize register file read ports.
  10. Ishikawa Isako (Tokyo JPX) Ushimaru Yumiko (Tokyo JPX), Parallel pipelined instruction processing system for very long instruction word.
  11. Matsuzaki Toshimichi (Minoh JPX) Higaki Nobuo (Osaka JPX) Deguchi Masashi (Nara JPX), Pipeline data processor with arithmetic/logic unit capable of performing different kinds of calculations in a pipeline s.
  12. Kumar Rajendra (Sunnyvale CA) Emerson Paul G. (San Jose CA), Scalable register file organization for a computer architecture having multiple functional units or a large register fil.
  13. Dowling Eric M., Split embedded DRAM processor.
  14. Rau Bantwal R. (Los Gatos CA) Towle Ross A. (Union City CA) Yen David W. (Cupertino CA) Yen Wei-Chen (Cupertino CA), System for selectively communicating instructions from memory locations simultaneously or from the same memory locations.
  15. Masubuchi Yoshio (Kawasaki JPX), Very large instruction word type computer for performing a data transfer between register files through a signal line pa.

이 특허를 인용한 특허 (77)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Leedy, Glenn J, Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer.
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Hughes, William A.; Yang, Chenping; Fertig, Michael K., Crossbar switch with primary and secondary pickers.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Leedy, Glenn J, Flexible and elastic dielectric integrated circuit.
  26. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Leedy, Glenn J, Lithography device for semiconductor circuit pattern generation.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  35. Leedy,Glenn J, Membrane 3D IC fabrication.
  36. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  37. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  46. Leedy,Glenn J, Method of information processing using three dimensional integrated circuits.
  47. Leedy,Glenn J, Method of making an integrated circuit.
  48. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  49. Leedy,Glenn J, Methods for maskless lithography.
  50. Steiss, Donald E.; Hoyle, David, Microprocessor with conditional cross path stall to minimize CPU cycle time length.
  51. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  52. Fetzer, Eric S.; Soltis, Jr., Donald C.; Undy, Stephen R., Register renaming to reduce bypass and increase apparent physical register size.
  53. Leedy, Glenn J., Stacked integrated memory device.
  54. Master,Paul L.; Watson,John, Storage and delivery of device features.
  55. Leedy, Glenn J, Stress-controlled dielectric integrated circuit.
  56. Leedy, Glenn Joseph, Stress-controlled dielectric integrated circuit.
  57. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  58. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  59. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  60. Leedy, Glenn J, Three dimension structure memory.
  61. Leedy, Glenn J, Three dimensional memory structure.
  62. Leedy, Glenn J, Three dimensional memory structure.
  63. Leedy, Glenn J, Three dimensional multi layer memory and control logic integrated circuit structure.
  64. Leedy,Glenn J, Three dimensional structure integrated circuit.
  65. Leedy, Glenn J, Three dimensional structure memory.
  66. Leedy, Glenn J, Three dimensional structure memory.
  67. Leedy, Glenn J., Three dimensional structure memory.
  68. Leedy, Glenn J., Three dimensional structure memory.
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  70. Leedy, Glenn J., Three dimensional structure memory.
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