초록 ▼

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the inventi

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for forming an inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electri

[ What is claimed is:] [1.]1. A method for forming an inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;depositing a passivation layer over said overlaying interconnecting metalization structure;depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;forming openings through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been -provided in or on the surface of said overlaying interconnecting metalization structure;filling said openings with a conductive material, creating metal contacts through said openings; andforming said inductor on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure.