초록 ▼

A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, sai

A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic. Positioning a plurality of said chips on a support in a deposition apparatus and preferably using chemical vapor deposition or sputtering techniques, a layer, or a sandwich of layers, of moisture-impermeable material is deposited on all edge sides simultaneously while preventing deposition of said material on at least portion of the exposed active or passive surfaces.

대표청구항 ▼

[ We claim:] [1.]1. A semiconductor device comprising:a semiconductor chip having an active and a passive surface and four edge sides, each edge side having substantially only a single plane;said active surface having an integrated circuit including multiple deposited layers and a plurality of conta

[ We claim:] [1.]1. A semiconductor device comprising:a semiconductor chip having an active and a passive surface and four edge sides, each edge side having substantially only a single plane;said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surfaces;said deposited layers having exposed portions at said edge sides;a protective overcoat impermeable to moisture overlying said integrated circuit; anda continuous sealant layer impermeable to moisture overlying all areas of said four edge sides, whereby said edge sides are sealed and said chip is rendered entirely hermetic.