초록 ▼

A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric l

A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric layer, a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. The bond frame structure, which is formed in a spaced apart relationship from the metal bond pad layer contains a plurality of island elements formed on top of the middle dielectric layer and an interconnected frame element formed on top of the top dielectric layer. The frame element contains a portion which overlaps with a portion of the metal bond pad layer, so as to exert a downward force to prevent the metal bond pad layer from peeling off. Each of the island elements is respectively connected to the underlying layer and the frame element by one or a plurality of hole-fills, which can contain an appropriate hole-material such as tungsten plus or can be filled with the same material constituting the layer overlaying them. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for fabricating a bond pad structure for use in an integrated circuit comprising the steps of:(a) forming a bottom dielectric layer on a wafer;(b) forming an underlying layer on top of said bottom dielectric layer;(c) forming a middle dielectric layer on top of

[ What is claimed is:] [1.]1. A method for fabricating a bond pad structure for use in an integrated circuit comprising the steps of:(a) forming a bottom dielectric layer on a wafer;(b) forming an underlying layer on top of said bottom dielectric layer;(c) forming a middle dielectric layer on top of said underlying layer, wherein said middle dielectric layer contains at least one first through-hole away from an area intended to form a metal bond pad layer;(d) filling said at least one first through-hole with a hole-fill material, and, either simultaneously or subsequently with respect thereof, forming said metal bond pad layer and an island element in said middle dielectric layer, said island element being spaced apart from said metal bond pad layer and in contact with said underlying layer through said filled first through-hole;(e) forming a top dielectric layer on top of said metal bond layer, wherein said top dielectric layer contains at least one second through-hole which is connected to said island element;(f) filling said at least one second through-hole, and, either simultaneously or subsequently with respect thereof, forming at least one frame element on top of said top dielectric vertically above said island element, wherein said island element and said frame element are substantially smaller than said metal bond pad layer, said frame element is formed to contain a portion whose vertical projection overlaps a portion of said metal bond pad layer, and said frame element is connected to said island element through said filled second through-hole.