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Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0483934 (2000-01-18)
발명자 / 주소
  • Huang Yung-Sheng,TWX
  • Lin Chiu-Ching,TWX
  • Lu Chun-Hung,TWX
  • Hwang Ruey-Lian,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 33  인용 특허 : 2

초록

A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying t

대표청구항

[ What is claimed is:] [1.]1. A method of creating a bond pad structure, on a semiconductor substrate, comprising the steps of:providing an upper level, metal interconnect structure, overlying, and contacting, underlying conductive regions, on, or in, said semiconductor substrate;forming an inter-me

이 특허에 인용된 특허 (2)

  1. Kuo Chien-Li,TWX, Bonding-pad structure for integrated circuit and method of fabricating the same.
  2. Hsiao Yung-Kuan,TWX ; Wu Cheng-Ming,TWX ; Lee Yu-Hua,TWX, Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings.

이 특허를 인용한 특허 (33)

  1. Bhatt, Hemanshu; Vijay, Dilip; Pallinti, Jayanthi; Sun, Sey-Shing; Ying, Hong; Kao, Chiyi, Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.
  2. Tran, Tu-Anh N.; Clegg, David B.; Safai, Sohrab, Bond pad and passivation layer having a gap and method for forming.
  3. Safai, Sohrab; Clegg, David B.; Tran, Tu-Anh N., Bond pad having a trench and method for forming.
  4. Chen,Hsien Wei, Bond pad structure for integrated circuit chip.
  5. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.
  6. Weng, Wu-Te; Nieh, Ji-Shyang, Chip pad resistant to antenna effect and method.
  7. Weng, Wu-Te; Nieh, Ji-Shyang, Chip pad resistant to antenna effect and method.
  8. Weng, Wu-Te; Nieh, Ji-Shyang, Chip pad resistant to antenna effect and method.
  9. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  10. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  11. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  12. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  13. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  14. Yamamoto,Koji; Kumamoto,Nobuhisa; Matsumoto,Muneyuki, Damascene interconnection and semiconductor device.
  15. Tran, Tu-Anh N.; Lee, Chu-Chung, Electronic component package and method for forming same.
  16. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  17. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.
  18. Angell, David; Beaulieu, Frederic; Hisada, Takashi; Kelly, Adreanne; McKnight, Samuel Roy; Miyai, Hiromitsu; Petrarca, Kevin Shawn; Sauter, Wolfgang; Volant, Richard Paul; Weinstein, Caitlin W., Internally reinforced bond pads.
  19. Angell,David; Beaulieu,Frederic; Hisada,Takashi; Kelly,Adreanne; McKnight,Samuel Roy; Miyai,Hiromitsu; Petrarca,Kevin Shawn; Sauter,Wolfgang; Volant,Richard Paul; Weinstein,Caitlin W., Internally reinforced bond pads.
  20. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.
  21. Kobayashi, Thomas S.; Pozder, Scott K., Method of forming a bond pad and structure thereof.
  22. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  23. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  24. Coolbaugh, Douglas D.; He, Zhong-Xiang; Sauter, Wolfgang; Waterhouse, Barbara A., Optimum padset for wire bonding RF technologies with high-Q inductors.
  25. Coolbaugh,Douglas D.; He,Zhong Xiang; Sauter,Wolfgang; Waterhouse,Barbara A., Optimum padset for wire bonding RF technologies with high-Q inductors.
  26. Chen, Hsien-Wei; Wu, Anbiarshy; Hsu, Shih-Hsun; Hou, Shang-Yun; Chen, Hsueh-Chung; Jeng, Shin-Puu, Pad structure design with reduced density.
  27. Li,Yuan, Pad structures to improve board-level reliability of solder-on-pad BGA structures.
  28. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.
  29. Toyoda, Hiroshi; Nakao, Mitsuhiro; Hasunuma, Masahiko; Kaneko, Hisashi; Sakata, Atsuko; Komukai, Toshiaki, Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device.
  30. Yang, Ming-Hsien; Wang, Ching-Chun; Yaung, Dun-Nian; Hung, Feng-Chi; Huang, Sin-Yao, Semiconductor device structure and method for forming the same.
  31. Bachman, Mark A.; Bitting, Donald S.; Chittipeddi, Sailesh; Kang, Seung H.; Merchant, Sailesh M., Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore.
  32. Yiu,Ho Yin; Fan,Fu Jier; Wu,Yu Jui; Wang,Aaron; Wang,Hsiang Wei; Lin,Huang Sheng; Chen,Ming Hsien; Shiue,Ruey Yun, Top via pattern for bond pad structure.
  33. Gumaste,Vijaylaxmi; Poddar,Anindya, Under-bond pad structures for integrated circuit devices.
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