IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0483934
(2000-01-18)
|
발명자
/ 주소 |
- Huang Yung-Sheng,TWX
- Lin Chiu-Ching,TWX
- Lu Chun-Hung,TWX
- Hwang Ruey-Lian,TWX
|
출원인 / 주소 |
- Taiwan Semiconductor Manufacturing Company, TWX
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
33 인용 특허 :
2 |
초록
▼
A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying t
A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying the bond pad structure, while overlying, and contacting, an underlying upper level, metal interconnect structure. The use of a tungsten mesh pattern, in place of individual tungsten studs, results in the creation of isolated islands, of IMED, reducing the bonding force, experienced by the IMD shapes, during the subsequent gold wire bond procedure. In addition the tungsten mesh pattern is formed via partial filling of a mesh pattern opening, in the IMD layer, resulting in an indented, or notched top surface. This in turn allows a roughened top surface, for the overlying bond pad structure, to be created, resulting in improved bondability of the gold wire, to the roughened top surface of the bond pad structure.
대표청구항
▼
[ What is claimed is:] [1.]1. A method of creating a bond pad structure, on a semiconductor substrate, comprising the steps of:providing an upper level, metal interconnect structure, overlying, and contacting, underlying conductive regions, on, or in, said semiconductor substrate;forming an inter-me
[ What is claimed is:] [1.]1. A method of creating a bond pad structure, on a semiconductor substrate, comprising the steps of:providing an upper level, metal interconnect structure, overlying, and contacting, underlying conductive regions, on, or in, said semiconductor substrate;forming an inter-metal dielectric, (IMD), layer, on said upper level, metal interconnect structure;performing an etching procedure to create a mesh pattern opening, in said IMD layer, exposing regions of the top surface of said upper level, metal interconnect structure, and creating unetched, isolated islands of said IMD layer,depositing a metal layer, on the top surface of said isolated islands of said IMD layer, and partially filling said mesh pattern opening;removing portions of said metal layer from the top surface of said isolated islands of said IMD layer, creating a metal mesh structure, in said mesh pattern opening, with the metal mash structure featuring a notched, or indented top surface, resulting from the partial metal fill of said mesh pattern opening;forming said bond pad structure, featuring a roughened top surface topography, as a result of the underlying notched, or indented surface, of said metal mesh structure; andforming a wire bond on said bond pad structure.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.