$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

특허 상세정보

Reconfigurable test system

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-009/44    G06F-013/10    G06F-013/12    G06F-009/455   
미국특허분류(USC) 703/021 ; 703/023
출원번호 US-0229695 (1999-01-13)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Conley, Rose & Tayon, PCHood
인용정보 피인용 횟수 : 163  인용 특허 : 13
초록

A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware--i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium--and optionally, an embedded processor. A user specifies system features with a software configuration utility whic...

대표
청구항

[ We claim:] [1.]1. A reconfigurable test system comprising:a computer system which includes a host CPU and host memory, wherein the host memory stores a hardware architecture library, a driver component library, a configuration utility, and a software driver, wherein the hardware architecture library comprises a plurality of hardware architecture files, wherein the driver component library comprises a plurality of software driver modules;an instrument coupled to the computer system, wherein the instrument includes a reconfigurable hardware module, where...

이 특허에 인용된 특허 (13)

  1. Tredennick Harry L. (Los Gatos CA) Van den Bout David E. (Apex NC). Baseboard and daughtercard apparatus for reconfigurable computing systems. USP1996125583749.
  2. Terasima Junichi (Tokyo JPX) Asai Toshinori (Tokyo JPX) Kawahori Masaki (Chiba JPX). Data reading and image processing system for CD-ROM. USP1995085437464.
  3. Cypher Allen (Palo Alto CA) Smith David C. (Saratoga CA) Spohrer James C. (Santa Clara CA). Extensible simulation system and graphical programming method. USP1996105566295.
  4. Casselman Steven Mark (Reseda CA). FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in. USP1997115684980.
  5. Kodosky Jeffrey L. (Austin TX) Truchard James J. (Austin TX) MacCrisken John E. (Palo Alto CA). Graphical system for modelling a process and associated method. USP1990024901221.
  6. Littleton James G. (Houston TX). Graphics program adaptor. USP1992045109504.
  7. Taylor Brad (Oakland CA). Implementation of a selected instruction set CPU in programmable hardware. USP1997075652875.
  8. Taylor Brad (Oakland CA). Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication. USP1996075535342.
  9. Mitchell Bob ; Andrade Hugo ; Pathak Jogen ; DeKey Samson ; Shah Abhay ; Brower Todd. System and method for controlling an instrumentation system. USP1998125847955.
  10. Sojoodi Omid ; Rust Scott A.. System and method for performing interface independent virtual instrumentation functions in a graphical data flow progr. USP1998075784275.
  11. Taylor Brad (Oakland CA) Dowling Robert (Albany CA). System for compiling algorithmic language source code for implementation in programmable hardware. USP1997025603043.
  12. Taylor Brad (Oakland CA). Video processing module using a second programmable logic device which reconfigures a first programmable logic device fo. USP1996035497498.
  13. Bhaskar Kasi S. (Seattle WA) Peckol James K. (Edmonds WA). Virtual machine programming system. USP1989074849880.

이 특허를 인용한 특허 피인용횟수: 163

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  10. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  11. Mar, Monte. Apparatus and method for programmable power management in a programmable analog circuit block. USP2012048149048.
  12. Anderson, Howard C.; Bersch, Danny Austin; Macbeth, Ian Craig; Schene, Christopher Robin; Streit, Timothy James. Apparatus for programming a programmable device, and method. USP2005126978435.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  18. Callaghan, David M.; Batke, Brian A.. Application and service management for industrial control devices. USP2010047693581.
  19. Abramovici,Miron. Assertion checking using two or more cores. USP2006117137086.
  20. Clarke,Jeffrey R.; Buckley,Robert M.; Silhan,Dean R.. Attenuator test system. USP2006067065466.
  21. Kuturianu,Olga; Rosenman,Victor. Automated test execution framework with central management. USP2008047366955.
  22. Callaghan, David M.. Automation device data interface. USP2009077565351.
  23. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G.. Autonomous control in a programmable system. USP2016099448964.
  24. Roe, Steve; Nemecek, Craig. Breakpoint control in an in-circuit emulation system. USP2012018103496.
  25. Anderson,Timothy M.; Baumann,Warren J.. Build time determination and installation of drivers on cloned systems. USP2008117448034.
  26. Wright, David G.; Williams, Timothy J.. Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes. USP2011118049569.
  27. Synder, Warren; Sullam, Bert. Clock driven dynamic datapath chaining. USP2013088516025.
  28. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  29. Nemecek, Craig. Conditional branching in an in-circuit emulation system. USP2010077765095.
  30. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  31. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat. Configuration of programmable IC design elements. USP2013078499270.
  32. Allstrom, Peter E.; Howe, Spencer K.. Configurator with embedded firmware for offline instrument user settings implementation. USP2014078776019.
  33. Cloury, Emmanuel; Grand, David; Oms, Patrick; Paulard, Michel. Connection system and simulator using such a connection system. USP2015119176189.
  34. Lee, Bang Won; Hwi, Kim Do. Connector and cable having transducer and receiver for optical transmission. USP2003016502997.
  35. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba. Consumer product distribution in the embedded system market. USP2010017644279.
  36. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  37. Vakrat,Yaniv; Rosenman,Victor. Dynamic distribution of test execution. USP2008027334162.
  38. Synder, Warren; Sullam, Bert. Dynamically configurable and re-configurable data path. USP2017029564902.
  39. Britch, Peter F.; Korpi, Emery. Electro-mechanical system simulator arrangement and method. USP2012088249845.
  40. Callaghan,David Michael. Embedded database systems and methods in an industrial controller environment. USP2008127467018.
  41. Nemecek, Craig; Roe, Steve. External interface for event architecture. USP2012018103497.
  42. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  43. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  44. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  45. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  46. Kanago, Kerwin D. Fast test application switching method and system. USP2003016512988.
  47. Pouchak, Michael A.; Smith, Gary A.. Graphical language compiler system. USP2013048418128.
  48. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat. Graphical user interface for dynamically reconfiguring a programmable device. USP2013098533677.
  49. Anderson, Doug. Graphical user interface with user-selectable list-box. USP2011128078970.
  50. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  51. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  52. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  53. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  54. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  55. Jiang, Tao; Xie, Xiaohua. Hardware test and diagnosis system and method. USP2014028660817.
  56. Wilt, Nicholas; Gray, Scott; Fletcher, Mitch. High integrity data bus fault detection using multiple signal components. USP2013018365024.
  57. Su, Peisheng Alan. Hybrid electronic design system and reconfigurable connection matrix thereof. USP2014068744832.
  58. Nemecek, Craig; Roe, Steve. In-circuit emulator and pod synchronized boot. USP2012048160864.
  59. Seguine, Dennis R.. Input/output multiplexer bus. USP2014058717042.
  60. Sequine, Dennis R.. Input/output multiplexer bus. USP2011118067948.
  61. Spinner, Robert; Leippe, William Harold; McKenna, James; Fox, Timothy. Instrumentation ATS/TPS mitigation utilizing I/O data stream. USP2013018359585.
  62. Odom,Brian Keith; Butler,Cary Paul; Willden,Jeremy. Instrumentation system having a reconfigurable instrumentation card with programmable logic and a modular daughter card. USP2006087089466.
  63. Chen,Chien Hsu. Interface device for product testing. USP2006037009380.
  64. Hite, Thomas D.; Barber, Ronald W.; Partridge, Charles W.; Lee, Mark R.; McGrane, William B.; Myer, Aaron L.; Lewno, Mark S.. Internet control system communication protocol, method and computer program. USP2013108572224.
  65. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  66. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  67. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  68. Kuturianu, Olga; Rosenman, Victor. Mechanism for executing test suites written for different harnesses under one test execution harness. USP2009067543275.
  69. Moyal, Nathan; Stiff, Jonathon. Method and circuit for rapid alignment of signals. USP2011027893724.
  70. Ward, Robert D.; Whapham, Robert Michael; Kessler, Joseph P.. Method and computer program for device configuration. USP2015069063739.
  71. Wagner, Horst; Stuerzl, Volker; Schöneck, Guenter; Breitenbach, legal representative, Gerda. Method and device for emulating control and/or regulating functions of a control or regulating device. USP2012058170860.
  72. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  73. Sanchez, Reno L.; Linn, John H.. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC). USP2009067552415.
  74. Sanchez,Reno L.; Linn,John H.. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC). USP2006026996796.
  75. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  76. Dale, Allan; Bayerl, Thomas; Mahaney, Craig. Method and system for integrating and controlling components and subsystems. USP2010037681201.
  77. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  78. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  79. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  80. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  81. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  82. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  83. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  84. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  85. Spinner, Robert; Levi, Eli; Leippe, William Harold; Korpi, Emery; Lai, Michael; Kuveikis, James; Chalmers, Richard E.; Engel, Richard; Britch, Peter F.; Biagiotti, William; Howell, David. Method and system for simulating test instruments and instrument functions. USP2012038131529.
  86. Spinner, Robert; Levi, Eli; Leippe, William Harold; Korpi, Emery; Lai, Michael; Kuveikis, James; Chalmers, Richard E.; Engel, Richard; Britch, Peter F.; Biagiotti, William; Howell, David. Method and system for simulating test instruments and instrument functions. USP2013078489381.
  87. Dittmann, Werner. Method for automatic programming, and associated components. USP2005096947799.
  88. Goodnow,Kenneth J.; Ogilvi챕,Clarence R.; Reynolds,Christ pher B.; Smith,Jack R.; Ventrone,Sebastian T.. Method for modifying the behavior of a state machine. USP2006067065733.
  89. Perrin, Jon; Seguine, Dennis. Method for parameterizing a user module. USP2010077761845.
  90. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  91. Bajohr, Colleen Y.; Handorf, Timothy; Gupta, Prashant. Methods and apparatus for generating a dynamic document. USP2013118578265.
  92. Handorf, Timothy William; Haussler, Christopher; Duffy, Martin Daniel. Methods and apparatus for maintaining business rules in a configuration system. USP2016129524506.
  93. Seymour, Brian. Methods and systems for testing evaluation modules. USP2011077984428.
  94. Seymour, William Brian. Methods and systems for testing evaluation modules. USP2010077761259.
  95. Snyder, Warren S.; Mar, Monte. Microcontroller programmable system on a chip. USP20190410248604.
  96. Snyder, Warren S.; Mar, Monte. Microcontroller programmable system on a chip. USP20180610007636.
  97. Snyder, Warren S.; Mar, Monte. Microcontroller programmable system on a chip. USP20190410261932.
  98. Snyder, Warren. Microcontroller programmable system on a chip with programmable interconnect. USP2013108555032.
  99. Snyder, Warren S. Microcontroller programmable system on a chip with programmable interconnect. USP2017099766650.
  100. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug. Model for a hardware device-independent method of defining embedded firmware for programmable systems. USP2012108286125.
  101. Woods,Stanley P.; Sitte,Hans J.; Hamilton,Bruce. Modular system with synchronized timing. USP2006016983391.
  102. Mohammadian, Ali M.; Royle, David J.. Modular test instrument. USP2004056738454.
  103. Nakaya,Kazuyoshi. Module-testing device. USP2009037502706.
  104. Kutz, Harold. Numerical band gap. USP2012038130025.
  105. Snyder, Warren S.; Mar, Monte. PSOC architecture. USP2017129843327.
  106. Snyder, Warren; Mar, Monte. PSOC architecture. USP2014058736303.
  107. Snyder, Warren S.; Mar, Monte. PSoC architecture. USP20180710020810.
  108. Snyder, Warren S.; Mar, Monte. PSoC architecture. USP2018049954528.
  109. Vakrat,Yaniv; Rosenman,Victor. Parallel text execution on low-end emulators and devices. USP2007117296190.
  110. Granny,Nicola V.; Brisudova,Martina M.. Polymorphic computational system and method in signals intelligence analysis. USP2008067386833.
  111. Ogami, Kenneth Y.. Power management architecture, method and configuration system. USP2011128078894.
  112. Ogami, Kenneth Y.. Power management architecture, method and configuration system. USP2014128909960.
  113. Ganzert,Johannes. Process for distribution of a program code to a plurality of measuring instruments. USP2007027181385.
  114. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  115. Mar, Monte. Programmable analog system architecture. USP2005096941336.
  116. Ward, Derek. Programmable controller for use with monitoring device. USP2010037672738.
  117. Ward, Derek. Programmable logic controller and related electronic devices. USP2009117612582.
  118. Snyder, Warren. Programmable microcontroller architecture. USP2012058176296.
  119. Snyder, Warren; Mar, Monte. Programmable microcontroller architecture(mixed analog/digital). USP2010117825688.
  120. Snyder, Warren; Mar, Monte. Programmable microcontroller architecture(mixed analog/digital). USP2013018358150.
  121. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte. Programmable sigma-delta analog-to-digital converter. USP2011108040266.
  122. Mar,Monte; Snyder,Warren. Programming architecture for a programmable analog system. USP2006087092980.
  123. Terrill, Richard Shaw; Bielby, Robert Richard Noel. Programming circuits and techniques for programmable logic. USP2003106636936.
  124. Caltagirone, Christophe R. J.; Vazquez, Nicolas F.; Nair, Dinesh; Buchanan, Bradley D.; Jenson, Jared W.; Schultz, Kevin L.. Prototyping an image processing algorithm and emulating or simulating execution on a hardware accelerator to estimate resource usage or performance. USP20190310235477.
  125. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark. Providing hardware independence to automate code generation of processing device firmware. USP2011118069436.
  126. Yoshida,Hiroshi; Kanno,Shinichi; Tomizawa,Takeshi; Namekata,Minoru; Tsurumi,Hiroshi; Tamada,Yuzo. Radio communicating apparatus, radio communicating method, and recording medium. USP2007027180934.
  127. Fletcher, Mitch; Sloat, Jef; Gregg, Michael R.. Re-configurable multi-purpose digital interface. USP2014078782299.
  128. John Morelli ; H. Richard Kendall. Reconfigurable logic for a computer. USP2002086438737.
  129. Odom,Brian Keith; Peck,Joseph E.; Andrade,Hugo A.; Butler,Cary Paul; Truchard,James J.; Petersen,Newton G.; Novacek,Matthew. Reconfigurable measurement system utilizing a programmable hardware element and fixed hardware resources. USP2006087085670.
  130. Andrade,Hugo A.; Odom,Brian Keith; Ryan,Arthur. Reconfigurable test system. USP2006127152027.
  131. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd. Reconfigurable testing system and method. USP2013038402313.
  132. Callaghan, David M.. Reliable messaging instruction. USP2010047706895.
  133. Callaghan, David M.. Reliable messaging instruction. USP2013038402101.
  134. Kortum,Philip T.; Brandt,Jeffrey T.. Restoring base configuration on software testing computer. USP2007097272549.
  135. Balasinski,Artur P.. Scheme for evaluating costs and/or benefits of manufacturing technologies. USP2007067231374.
  136. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas. Secure storage of program code for an embedded system. USP2010097802108.
  137. Rosenman,Victor; Kuturianu,Olga. Simultaneous execution of test suites on different platforms. USP2007107287190.
  138. Nemecek, Craig. Sleep and stall in an in-circuit emulation system. USP2010087774190.
  139. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  140. Peck,Joseph E.; Novacek,Matthew; Andrade,Hugo A.; Petersen,Newton G.. System and method for configuring a reconfigurable system. USP2007107290244.
  141. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat. System and method for controlling a target device. USP2017089720805.
  142. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Mihal, Andrew. System and method for converting graphical programs into hardware implementations which utilize probe insertion. USP2003066584601.
  143. Anderson, Douglas H.; Ogami, Kenneth Y.. System and method for dynamically generating a configuration datasheet. USP2010087770113.
  144. Steg,Sean C; Carroll,George A; Yue,David; Smith,Tracee. System and method for implementing maintenance functions for a switch. USP2007107284234.
  145. Ogami, Kenneth Y.; Hood, Frederick R.. System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit. USP2013028370791.
  146. Ogami, Kenneth Y.; Hood, III, Frederick R.. System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit. USP2010117844437.
  147. Aliphas,Amnon. System and method for testing hardware or software modules via a computer network. USP2008107444256.
  148. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  149. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  150. Sullam, Bert; Snyder, Warren; Mohammed, Haneef. System level interconnect with programmable switching. USP2013078476928.
  151. Sullam, Bert; Snyder, Warren; Mohammed, Haneef. System level interconnect with programmable switching. USP2011098026739.
  152. Boss, Gregory Jensen; Harding, Jonathan Thomas; Hamilton, II, Rick Allen; Waters, Timothy Moffett. Systems and methods for embedded application test suites. USP2010117836432.
  153. Motamed, Margaret; Someshwar, Ravi; Kong, Chew Yan; Gunturu, Ravindranath. Systems and methods for multiple raster image processing. USP2011027884962.
  154. McGettigan,Edward S.; Fross,Bradley K.; Peattie,Michael E.. Systems and methods of utilizing virtual input and output modules in a programmable logic device. USP2006087085706.
  155. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  156. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding. Techniques for generating microcontroller configuration information. USP2011118069428.
  157. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick. Techniques for generating microcontroller configuration information. USP2014078793635.
  158. Venkataraman, Garthik; Kutz, Harold; Mar, Monte. Temperature sensor with digital bandgap. USP2012018092083.
  159. Shulz, Bradley Dean; Buth, Michael Ray; Breece, Jeffrey Allan; Tillman, David Martin; Bitney, Maureen; Bennington, Darrell Robert; Patel, Pinkiekumar D.. Testing machine with graphical user interface with situational awareness. USP2018029904258.
  160. Beard, Paul; Woodings, Ryan Winfield. Touch wake for electronic devices. USP2012018089461.
  161. Fletcher, Mitch; Kreider, Thom; Wilt, Nicholas. Universal functionality module. USP2013038390324.
  162. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug. User interface for efficiently browsing an electronic document using data-driven tabs. USP2011118069405.
  163. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar. Voltage controlled oscillator delay cell and method. USP2012028120408.