초록 ▼

A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to t

A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to the present invention, includes logic for allocating and deallocating two sets of rename registers, one set from a regular rename buffer and another set from an overflow rename buffer. According to this allocation/deallocation logic, if the oldest dispatched, noncompleted instruction is ready for assignment of a rename register and the regular rename buffer is full, then a rename register is assigned from the overflow rename buffer to this instruction.

대표청구항 ▼

[ What is claimed is:] [1.]1. A method of assigning rename registers to instructions being processed in a processor, comprising the steps of:dispatching instructions; andassigning, to a dispatched instruction having a target register, a rename register from among a plurality of rename registers, whe

[ What is claimed is:] [1.]1. A method of assigning rename registers to instructions being processed in a processor, comprising the steps of:dispatching instructions; andassigning, to a dispatched instruction having a target register, a rename register from among a plurality of rename registers, wherein the assigning of a rename register includes assigning the rename register in response to availability of source operands for the dispatched instruction.