$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereon

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/495
출원번호 US-0664341 (2000-09-18)
우선권정보 JP0062220 (2000-03-07)
발명자 / 주소
  • Yoshida Takanobu,JPX
  • Shinohara Toshiaki,JPX
  • Kawafuji Hisashi,JPX
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha, JPX
대리인 / 주소
    Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
인용정보 피인용 횟수 : 35  인용 특허 : 10

초록

A resin-sealed power semiconductor device is provided. The thicknesses of a die pad (19) and a lead part (2) are made equal and as great as possible. A thick film substrate (8) is bonded with a bonding layer (20) onto a plurality of supporting inner leads (2AS) among first inner leads (2A1) position

대표청구항

[ What is claimed is:] [1.]1. A resin-sealed power semiconductor device comprising:a frame part comprising a lead part having a plurality of inner leads and a plurality of outer leads continuous respectively with said plurality of inner leads, and a die pad equal in thickness to said lead part;a pow

이 특허에 인용된 특허 (10)

  1. Martinez Roberto ; Cheah Chuan, Co-packaged MOS-gated device and control integrated circuit.
  2. Tanaka Masao (Tottori JPX) Tanaka Kentaro (Tottori JPX) Hakata Kunihiko (Tottori JPX) Nishimura Susumu (Tottori JPX) Yamane Mikihito (Tottori JPX) Maeta Susumu (Tottori JPX), Light receiving module for converting light signal to electric signal.
  3. Masumoto Toshikazu,JPX ; Takahama Shinobu,JPX, Method of fabricating power semiconductor device and lead frame.
  4. Tagawa Tomohide (Kawanishi JPX) Takahashi Takashi (Kawanishi JPX) Kawakami Takayoshi (Itami JPX), Multiple-chip semiconductor device and a method of manufacturing the same.
  5. Sawaya Hiromichi (Kawasaki JPX), Resin-sealed type IC device.
  6. Noda Sukehisa,JPX ; Fujita Akira,JPX ; Yoshimatsu Naoki,JPX ; Takehara Makoto,JPX, Semiconductor device.
  7. Noda Sukehisa,JPX ; Yamada Shinji,JPX ; Iwagami Tooru,JPX ; Iwagaki Seiki,JPX ; Kawafuji Hisashi,JPX, Semiconductor device.
  8. Noda Sukehisa,JPX ; Yamada Shinji,JPX ; Iwagami Tooru,JPX ; Iwagaki Seiki,JPX ; Kawafuji Hisashi,JPX, Semiconductor device.
  9. Himeno Daichi (Kawanishi JPX) Kato Hazime (Itami JPX), Semiconductor device in a single package with high wiring density and a heat sink.
  10. Majumdar Gourab (Toyko JPX) Iwagami Tooru (Toyko JPX) Noda Sukehisa (Toyko JPX), Semiconductor power module.

이 특허를 인용한 특허 (35)

  1. Katsuyama,Tomokazu, AC coupling circuit having a large capacitance and a good frequency response.
  2. Liu, Chenglin; Liou, Shiann-Ming, Chip on leads.
  3. Sakamoto, Noriaki; Kobayashi, Yoshiyuki; Sakamoto, Junji; Mashimo, Shigeaki; Okawa, Katsumi; Maehara, Eiju; Takahashi, Kouji; Fukuda, Hirokazu; Etou, Hiroki, Circuit device and method of manufacturing the same.
  4. Takakusaki, Sadamichi; Sakamoto, Noriaki, Circuit device and method of manufacturing the same.
  5. Owyang, King; Kasem, Mohammed; Bai, Yuming; Kuo, Frank; Mao, Sen; Kuo, Sam, Complete power management system implemented in a single surface mount package.
  6. Owyang, King; Kasem, Mohammed; Bai, Yuming; Kuo, Frank; Mao, Sen; Kuo, Sam, Complete power management system implemented in a single surface mount package.
  7. Owyang, King; Kasem, Mohammed; Bai, Yuming; Kuo, Frank; Mao, Sen; Kuo, Sam, Complete power management system implemented in a single surface mount package.
  8. Otremba, Ralf; Schiess, Klaus, Compound semiconductor device including a multilevel carrier.
  9. Lo Verde, Domenico; Bruno, Giuseppe, Electric connection structure for electronic power devices, and method of connection.
  10. Sheng Tsung Liu TW, Electronic package with surface-mountable device built therein.
  11. Lee, Han-Hsiang; Shih, Kun-Hong; Li, Jeng-Jen, Electronic system with a composite substrate.
  12. Kuo, Frank, Encapsulation techniques for leadless semiconductor packages.
  13. Joshi, Rajeev, Flip chip in leaded molded package with two dies.
  14. Kim, Young Cheol; Lee, Koo Hong; Yee, Jae Hak, Integrated circuit package system with L-shaped leadfingers.
  15. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Tay, Lionel Chien Hui, Integrated circuit packaging system with plated leads and method of manufacture thereof.
  16. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Tay, Lionel Chien Hui, Integrated circuit packaging system with plated leads and method of manufacture thereof.
  17. Kuah, Hsian Pang; Phua, Jenny, Inverted lead frame in substrate.
  18. Shiraki, Satoshi; Yamada, Akira; Ban, Hiroyuki, Load driving device.
  19. Lee, Joo-sang; Jeon, O-seob; Kwon, Yong-suk; Chen, Frank; Zhu, Adams, Power device package.
  20. Takahashi, Keiko; Minamio, Masanori; Yamashita, Kenya, Power module.
  21. Zeng, Jian-Hong; Hong, Shou-Yu; Ye, Qi-Feng; Lin, Yi-Cheng, Power module.
  22. Lee, Keunhyuk; Jeon, Oseob; Lim, Seungwon, Power module package having excellent heat sink emission capability and method for manufacturing the same.
  23. Jeun,Gi young; Park,Sung min; Lee,Joo sang; Lim,Sung won; Jeon,O seob; Lee,Byoung ok; Kim,Young gil; Yang,Gwi gyeon, Power module package having improved heat dissipating capability.
  24. Jeun,Gi young; Park,Sung min; Lee,Joo sang; Lim,Sung won; Jeon,O seob; Lee,Byoung ok; Kim,Young gil; Yang,Gwi gyeon, Power module package having improved heat dissipating capability.
  25. Gi-young Jeon KR; Eul-bin Im KR; Byeong Gon Kim KR; Eun-ho Lee KR, Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereof.
  26. Liu,Chun Tiao; Chen,Da Jung; Lin,Chun Liang; Li,Jeng Jen; Hsu,Cheng Chieh; Wen,Chau Chun, Power module package structure.
  27. Shinohara, Toshiaki; Yoshida, Takanobu, Power semiconductor device with high radiating efficiency.
  28. Zeng, Jian-Hong; Hong, Shou-Yu; Guo, Xue-Tao, Power system, power module therein and method for fabricating power module.
  29. Minamio, Masanori; Ijima, Shinichi, Resin-sealed semiconductor device and method for fabricating the same.
  30. Kunimatsu,Takashi; Fukui,Minoru, Semiconductor device.
  31. Sakabe, Katsumi, Semiconductor device.
  32. Asano, Tetsuro; Sakakibara, Mikito; Inotsume, Hideyuki; Sakai, Haruhiko; Kimura, Shigeo, Semiconductor device and packaging system therefore.
  33. Cablao, Philip Lyndon R.; Filoteo, Jr., Dario S.; Espiritu, Emmanuel A.; Merilo, Leo A., Stacked die semiconductor device having circuit tape.
  34. Cablao, Philip Lyndon R.; Filoteo, Jr., Dario S.; Espiritu, Emmanuel A.; Merilo, Leo A., Stacked die semiconductor device having circuit tape.
  35. Lee, Keun-hyuk; Jeun, Gi-Young; Jeon, O-seob, Three-dimensional power semiconductor module and method of manufacturing the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트