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Coaxial integrated circuitry interconnect lines, and integrated circuitry 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0118346 (1998-07-17)
발명자 / 주소
  • Geusic Joseph E.
  • Ahn Kie Y.
  • Forbes Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells, St. John, Roberts, Gregory & Matkin, P.S.
인용정보 피인용 횟수 : 53  인용 특허 : 52

초록

Methods of forming integrated circuitry lines such as coaxial integrated circuitry interconnect lines, and related integrated circuitry are described. An inner conductive coaxial line component is formed which extends through a substrate. An outer conductive coaxial line component and coaxial dielec

대표청구항

[ What is claimed is:] [1.]1. Integrated circuitry comprising a bulk semiconductive substrate having front and back surfaces and a plurality of conductive coaxial interconnect lines extending through the substrate from the front surface to the back surface; the conductive coaxial interconnect lines

이 특허에 인용된 특허 (52)

  1. Anthony Thomas R. (Schenectady NY), Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers.
  2. Aizawa Yoshiaki (Kanagawa-ken JPX) Katoh Toshimitu (Kanagawa-ken JPX), Bidirectional semiconductor switch.
  3. Esquivel Agerico L. (13912 Waterfall Way Dallas TX 75240) Mitchell Allan T. (2913 Green Meadow Garland TX 75042), Buried multilevel interconnect system.
  4. Hawkins Richard E. (Colchester VT), Coaxial cables.
  5. Chen Sen-Fu,TWX ; Wu Jie-Shing,TWX ; Chen Fang-Cheng,TWX ; Lee Tsung-Tser,TWX, Damage free passivation layer etching process.
  6. Anthony Thomas R. (Schenectady NY) Cline Harvey E. (Schenectady NY), Deep diode lead throughs.
  7. Goldstein Edward F. (373 Western Dr. ; #H Santa Cruz CA 95060-3053), Electrically conductive interconnection through a body of semiconductor material.
  8. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
  9. Bertin Claude Louis ; Howell Wayne John ; Tonti William Robert Patrick ; Zalesnski Jerzy Maria, Integrated high-performance decoupling capacitor.
  10. Hong Gary (Hsinchu TWX), Interconnection with self-aligned via plug.
  11. Adamic ; Jr. Fred W., Inverted dielectric isolation process.
  12. Rostoker Michael D. (Boulder Creek CA) Kapoor Ashok K. (Palo Alto CA), Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures.
  13. Yang Sheng-Hsing (Hsinchu TWX), Method for fabricating a bipolar power transistor.
  14. Lin Dahcheng,TWX ; Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX, Method for fabricating a stacked, or crown shaped, capacitor structure.
  15. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  16. White David M. (Sulpher Springs TX), Method for manufacturing a coaxial interconnect.
  17. Jain Ajay, Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer.
  18. Anthony Thomas R. (Schenectady NY) Houston Douglas E. (Liverpool NY) Loughran James A. (Scotia NY), Method for producing high-aspect ratio hollow diffused regions in a semiconductor body.
  19. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  20. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
  21. Kanber Hilda (Rolling Hills Estates CA), Method of fabricating three dimensional gallium arsenide microelectronic device.
  22. Gaul Stephen J. (Melbourne FL), Method of fabrication of surface mountable integrated circuits.
  23. Koh Wei H. (Irvine CA) McCausland Connie S. (San Juan Capistrano CA), Method of forming a microcircuit via interconnect.
  24. Soclof Sidney I. (San Gabriel CA), Method of forming lateral bipolar transistors.
  25. Gurtler Richard W. (Mesa AZ) Pearse Jeffrey (Chandler AZ) Wilson Syd R. (Phoenix AZ), Method of forming vias through two-sided substrate.
  26. Gardner Mark I. ; Spikes ; Jr. Thomas E. ; Paiz Robert ; Hause Frederick N. ; Sun Sey-Ping, Method of manufacturing a semiconductor device using advanced contact formation.
  27. Koh Wei H. ; McCausland Connie S., Microcircuit via interconnect.
  28. Mochizuki Masao (Yokohama JPX), Microwave integrated circuit (MIC) having a reactance element formed on a groove.
  29. Nakano Hirofumi (Itami JPX), Multi-layer wiring.
  30. Bass ; Jr. Roy S. (Underhill VT) Bhattacharyya Arup (Essex Junction VT) Grise Gary D. (Colchester VT), Non-volatile memory cell having Si rich silicon nitride charge trapping layer.
  31. Miles Robert S. ; Trask Philip A. ; Pillai Vincent A., Phase mask laser fabrication of fine pattern electronic interconnect structures.
  32. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  33. Minahan Joseph A. (Simi Valley CA) Ralph Eugene L. (San Gabriel CA) Dill Hans G. (Newhall CA), Process for fabricating a wraparound contact solar cell.
  34. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
  35. Finnila Ronald M. (Carlsbad CA), Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substr.
  36. Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
  37. Roberts Martin C. (Boise ID), Semiconductor device.
  38. Koseki Osamu,JPX ; Ishii Takichi,JPX ; Mandai Masaaki,JPX ; Yoshino Tomoyuki,JPX ; Takeuchi Hitoshi,JPX, Semiconductor device having a trapezoidal joint chip.
  39. Inoue Tomotoshi (Kanagawa JPX) Terada Toshiyuki (Tokyo JPX) Tomita Kenichi (Kanagawa JPX), Semiconductor device having an improved air-bridge lead structure.
  40. Mikagi Kaoru (Tokyo JPX), Semiconductor device having an interconnection of a laminate structure and a method for manufacturing the same.
  41. Vallett David P., Semiconductor devices having backside probing capability.
  42. Tsunemine Yoshikazu (Hyogo JPX), Semiconductor memory device and manufacturing method thereof.
  43. Ichihashi Motomi,JPX, Semiconductor sensor with protective cap covering exposed conductive through-holes.
  44. Tanielian Minas H. (Bellevue WA), Silicon wafers containing conductive feedthroughs.
  45. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
  46. Chang Mike F. ; Owyang King ; Hshieh Fwu-Iuan ; Ho Yueh-Se ; Dun Jowei, Surface mount and flip chip technology for total integrated circuit isolation.
  47. Gaul Stephen Joseph ; Delgado Jose Avelino, Surface mount die by handle replacement.
  48. Gaul Stephen Joseph (Melbourne FL), System for interconnecting stacked integrated circuits.
  49. Yamaga Kenichi,JPX ; Mikata Yuichi,JPX ; Yamamoto Akihito,JPX, Thermal processing method and apparatus therefor.
  50. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
  51. Bauer Friedhelm (Baden CHX) Vuilleumier Raymond (Fontainemelon CHX), Turn-off, MOS-controlled, power semiconductor component.
  52. Cronin John E. (Milton VT) Leach Michael A. (Colchester VT), VLSI coaxial wiring structure.

이 특허를 인용한 특허 (53)

  1. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  2. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  3. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  4. Akram, Salman; Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection.
  5. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  6. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  7. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  8. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  9. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  10. Akram,Salman; Ahn,Kie Y.; Forbes,Leonard, High permeability layered magnetic films to reduce noise in high speed interconnection.
  11. Kohl, Paul A.; He, Ate; Cupta, Mark; Bakir, Muhannad; Spencer, Todd, Integrated circuit interconnects with coaxial conductors.
  12. Kirby,Kyle K., Interconnect having spring contacts.
  13. Benson, Peter A.; Watkins, Charles M., Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies.
  14. Kirby,Kyle K., Method for creating electrical pathways for semiconductor device structures using laser machining processes.
  15. Benson, Peter A.; Watkins, Charles M., Method for creating electrically conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies.
  16. Kirby,Kyle K., Method for fabricating an interconnect for semiconductor components.
  17. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung Tri, Method for fabricating encapsulated semiconductor components.
  18. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Method for fabricating encapsulated semiconductor components.
  19. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Method for fabricating encapsulated semiconductor components having conductive vias.
  20. Wood,Alan G.; Doan,Trung Tri, Method for fabricating semiconductor component with thinned substrate having pin contacts.
  21. Wood,Alan G.; Doan,Trung Tri, Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side contacts.
  22. Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts.
  23. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung Tri, Method of fabricating encapsulated semiconductor components by etching.
  24. Ahn, Kie Y.; Forbes, Leonard, Methods for atomic-layer deposition.
  25. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates.
  26. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates.
  27. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures.
  28. Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Multi-dice chip scale semiconductor components.
  29. Farnworth, Warren M.; Wood, Alan G.; Hiatt, William M.; Wark, James M.; Hembree, David R.; Kirby, Kyle K.; Benson, Pete A., Multi-dice chip scale semiconductor components and wafer level methods of fabrication.
  30. Mastromatteo, Ubaldo; Ferrari, Paolo, Process for manufacturing a through insulated interconnection in a body of semiconductor material.
  31. Mastromatteo,Ubaldo; Ferrari,Paolo, Process for manufacturing a through insulated interconnection in a body of semiconductor material.
  32. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Semiconductor assemblies having electrophoretically insulated vias.
  33. Wood,Alan G.; Doan,Trung Tri, Semiconductor component and assembly having female conductive members.
  34. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component and system having thinned, encapsulated dice.
  35. Wood, Alan G.; Doan, Trung Tri, Semiconductor component having backside pin contacts.
  36. Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having multiple stacked dice.
  37. Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate and stacked dice.
  38. Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate, stacked dice and conductive vias.
  39. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts.
  40. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts.
  41. Wood,Alan G.; Doan,Trung Tri, Semiconductor component having thinned substrate, backside pin contacts and circuit side contacts.
  42. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component sealed on five sides by polymer sealing layer.
  43. Wood, Alan G.; Doan, Trung Tri, Semiconductor component with backside contacts and method of fabrication.
  44. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung Tri, Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors.
  45. Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, Semiconductor components having stacked dice.
  46. Kirby,Kyle K., Semiconductor interconnect having semiconductor spring contacts.
  47. Farnworth,Warren M.; Collins,Dale W.; McDonald,Steven M., Semiconductor structures having electrophoretically insulated vias.
  48. Klein,Dean A.; Wood,Alan G.; Doan,Trung Tri, System having semiconductor component with multiple stacked dice.
  49. Kirby,Kyle K., Test system and test method with interconnect having semiconductor spring contacts.
  50. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  51. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  52. Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Wafer level methods for fabricating multi-dice chip scale semiconductor components.
  53. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Wafer level semiconductor component having thinned, encapsulated dice and polymer dam.
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