초록 ▼

A power switching circuit with reduced interference radiation includes at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected. One or at least one of the low-side MOS power transistors is connected to a drive circuit having a divider for dividin

A power switching circuit with reduced interference radiation includes at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected. One or at least one of the low-side MOS power transistors is connected to a drive circuit having a divider for dividing a difference between a maximum output voltage of the MOS power transistor and an instantaneous output voltage at the load resistor as a dividend, by a maximum output voltage of the MOS power transistor as a divisor, and a level converter for generating a drive voltage for the MOS power transistor. The drive voltage is proportional to the quotient.

대표청구항 ▼

[ I claim:] [1.]1. A power switching circuit with reduced interference radiation, comprising:at least one MOS power transistor; anda drive circuit connected to said at least one MOS power transistor, said drive circuit configured for generating a drive voltage for driving said at least one MOS power

[ I claim:] [1.]1. A power switching circuit with reduced interference radiation, comprising:at least one MOS power transistor; anda drive circuit connected to said at least one MOS power transistor, said drive circuit configured for generating a drive voltage for driving said at least one MOS power transistor proportional to a quotient ofa difference between a maximum output voltage of said at least one MOS power transistor and an actual output voltage at said at least one MOS power transistor as a dividend of said quotient andthe maximum output voltage of said at least one MOS power transistor as a divisor of said quotient.