초록 ▼

A RC delay time stabilizing circuit of the present invention includes an inverter which inverts a periodic input signal, a RC delay unit which is charged/discharged in accordance with an output from the inverter, a pull-up MOS transistor connected between a source voltage terminal and an output term

A RC delay time stabilizing circuit of the present invention includes an inverter which inverts a periodic input signal, a RC delay unit which is charged/discharged in accordance with an output from the inverter, a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal, and an output unit which generates an output signal having an identical delay time in accordance with output levels of the inverter and the RC delay unit. Such RC delay time stabilizing circuit of the present invention decreases the charging time of the RC delay unit when a periodic signal is inputted, thus being able to maintain the same delay time in each cycle of the input signal.

대표청구항 ▼

[ What is claimed is:] [1.]1. A RC delay time stabilizing circuit, comprising:an inverter inverting a periodic input signal;a RC delay unit being charged/discharged in accordance with an output from the inverter;a pull-up MOS transistor connected between a source voltage terminal and an output termi

[ What is claimed is:] [1.]1. A RC delay time stabilizing circuit, comprising:an inverter inverting a periodic input signal;a RC delay unit being charged/discharged in accordance with an output from the inverter;a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal; andan output unit that generates an output signal which has a substantially uniform delay time relative to the periodic input signal in accordance with output levels of the inverter and the RC delay unit, wherein the output unit comprises,first to third MOS transistors serially connected between a first prescribed voltage and a second prescribed voltage, anda fourth MOS transistor connected in parallel to drains of the second and third MOS transistors and to an output terminal of the output unit, wherein gates of thefirst and fourth MOS transistors are connected with the output terminal of the RC delay unit.