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Dynamically inhibiting competing resource requesters in favor of above threshold usage requester to reduce response delay 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/18
출원번호 US-0835279 (2001-04-13)
발명자 / 주소
  • Chrysos George Z.
  • Snyder
  • II Wilson P.
출원인 / 주소
  • Compaq Computer Corporation
대리인 / 주소
    Hamilton Brook Smith & Reynolds, P.C.
인용정보 피인용 횟수 : 17  인용 특허 : 13

초록

A method of limiting, in a digital processor, low-priority utilization of a resource in favor of high-priority utilization of the resource comprises determining a value predictive of high-priority utilization of the resource. Low-priority utilization of the resource is inhibited if the determined pr

대표청구항

[ What is claimed is:] [2.]2. In a computer system, a method for arbitrating among a plurality of requesters of resources, comprising the steps of:maintaining a history of utilization by a first requester of a resource during program execution;predicting, based on the utilization history, utilizatio

이 특허에 인용된 특허 (13)

  1. McKeen Francis X. (Westborough MA) Adler Michael C. (Lexington MA) Emer Joel S. (Acton MA) Nix Robert P. (Concord MA) Sager David J. (Acton MA) Lowney P. Geoffrey (Concord MA), Apparatus and method for speculatively executing instructions in a computer system.
  2. Boldt Gerald D. (Longmont CO) Hanna Stephen D. (Boulder CO), Arbitration system limiting high priority successive grants.
  3. Liptay John Stephen ; Check Mark Anthony ; Krumm Barry Watson ; Navarro Jennifer Almoradie ; Webb Charles Franklin, Computer with optimizing hardware for conditional hedge fetching into cache storage.
  4. Puziol David L. (Sunnyvale CA) Van Dyke Korbin S. (Fremont CA) Widigen Larry (Salinas CA) Shar Len (Menlo Park CA) Smith ; III Walstein B. (San Jose CA), Configurable branch prediction for a processor performing speculative execution.
  5. Levitan David S. (Austin TX), Counter register implementation for speculative execution of branch on count instructions.
  6. Ellsworth James G. (St. Paul MN) Wulling Thomas E. (St. Paul MN), Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to.
  7. Lentz Derek J. ; Hagiwara Yasuaki ; Lau Te-Li ; Tang Cheng-Long ; Nguyen Le Trong, Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied.
  8. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  9. Popescu Valeri (San Diego CA) Schultz Merle A. (Escondido CA) Gibson Gary A. (Carlsbad CA) Spracklen John E. (San Diego CA) Lightner Bruce D. (San Diego CA), Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which a.
  10. Popescu Valeri (San Diego CA) Schultz Merle A. (Escondido CA) Gibson Gary A. (Carlsbad CA) Spracklen John E. (San Diego CA) Lightner Bruce D. (San Diego CA), Processor architecture providing out-of-order execution.
  11. Popescu Valeri (San Diego CA) Schultz Merle A. (Escondido CA) Gibson Gary A. (Carlsbad CA) Spracklen John E. (San Diego CA) Lightner Bruce D. (San Diego CA), Processor architecture supporting multiple speculative branching.
  12. Emer Joel S. ; Stamm Rebecca ; Fossum Trggve ; Halstead ; Jr. Robert H. ; Chrysos George Z. ; Tullsen Dean ; Eggers Susan ; Levy Henry M., Thread properties attribute vector based thread selection in multithreading processor.
  13. Glew Andrew F. (Hillsboro OR) Akkary Haitham (Portland OR) Hinton Glenn J. (Portland OR), Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of proce.

이 특허를 인용한 특허 (17)

  1. Sultan,Robert; Sahai,Ajay; Pandhi,Sushil; Yang,Zubao, Aggregate rate transparent LAN service for closed user groups over optical rings.
  2. Young, Mark S., Arbitration and crossbar device and method.
  3. Rappoport, Lihu; Ronen, Ronny, Controlling population size of confidence assignments.
  4. Biswas, Sukalpa; Chen, Hao; Wadhawan, Ruchi, Dynamic QoS upgrading.
  5. Biswas, Sukalpa; Chen, Hao; Wadhawan, Ruchi, Dynamic QoS upgrading.
  6. Jagannathan, Ashok; Jain, Prabhat; Vinod, Krishna N.; Sodani, Avinash, Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources.
  7. Biswas, Sukalpa; Chen, Hao, Memory controller with QoS-aware scheduling.
  8. Ko, Yin Nam; Isherwood, Robert Graham, Method and apparatus for dynamic allocation of resources to executing threads in a multi-threaded processor.
  9. Shrader,Steven; Bishop,Wendy; Matta,Ashwin, Method and apparatus for multi-port memory controller.
  10. Yeager, Kenneth C., Method and system for prefetching data.
  11. Saund, Gurjeet S.; Balkan, Deniz; Wong, Kevin C., QoS inband upgrade.
  12. Biswas, Sukalpa; Chen, Hao, QoS-aware scheduling.
  13. Biswas, Sukalpa; Chen, Hao, QoS-aware scheduling.
  14. Biswas, Sukalpa; Chen, Hao, Reordering in the memory controller.
  15. Handlogten, Glen H.; Irish, John D., Resource allocation management using IOC token requestor logic.
  16. Fuchikami, Ryuji, Resource use management device, resource use management system, and control method for a resource use management device.
  17. Balkan, Deniz; Saund, Gurjeet S., Systems and methods for maintaining an order of read and write transactions in a computing system.
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