초록 ▼

An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical in

An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition. The PLD is configured to load the initial configuration bitstream from the PROM into the FPGA, and, responsive to the reconfiguration signal from the FPGA, to load a second configuration bitstream from the RAM into the FPGA. The control function may be configured to interact with standard network programs such as FTP (file transfer protocol) or custom programs.

대표청구항 ▼

[ What is claimed is:] [1.]1. A circuit arrangement for reconfiguration of an FPGA over a communications channel, comprising:a physical interface circuit arranged for connection to a communications channel;a storage element;an FPGA coupled to the storage element and to the physical interface circuit

[ What is claimed is:] [1.]1. A circuit arrangement for reconfiguration of an FPGA over a communications channel, comprising:a physical interface circuit arranged for connection to a communications channel;a storage element;an FPGA coupled to the storage element and to the physical interface circuit;a configuration control circuit coupled to the FPGA and to the storage element, the configuration control circuit being configured and arranged to load the FPGA with an initial configuration bitstream that implements both a communications protocol and a control function, wherein the control function writes configuration bits received by the FPGA from the physical interface circuit to the storage element and generates a reconfiguration signal responsive to a first predetermined condition, the configuration control circuit being further configured and arranged to load a second configuration bitstream from the storage element into the FPGA responsive to the reconfiguration signal from the FPGA.