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Method and apparatus for plating and polishing a semiconductor substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C25D-017/00
  • C25D-005/34
  • C25D-005/52
  • C25B-009/00
  • C25B-011/00
출원번호 US-0285621 (1999-04-03)
발명자 / 주소
  • Talieh Homayoun
  • Uzoh Cyprian Emeka
출원인 / 주소
  • Nutool, Inc.
대리인 / 주소
    Pillsbury Winthrop LLP
인용정보 피인용 횟수 : 127  인용 특허 : 19

초록 ▼

The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conducti

대표청구항 ▼

[ We claim:] [37.]37. A method of plating and removal of material from a surface of a semiconductor workpiece, the method comprising the steps of:plating a conductive material to the surface of the workpiece using an electrolyte solution disposed on the surface of the workpiece, the workpiece being

이 특허에 인용된 특허 (19)

  1. Kasashima Tatsuji (Toyanaka JPX) Morita Shuji (Kobe JPX) Hayami Hiroyuki (Itami JPX) Ose Seiroku (Higashiosaka JPX) Takada Yoshinori (Amagasaki JPX) Nozaki Fumihiro (Nishinomiya JPX), Apparatus for producing electrodeposited wires.
    상세보기
  2. Talieh Homayoun (San Jose CA), Chemical mechanical polishing apparatus with improved slurry distribution.
    상세보기
  3. Brusic Vlasta A. ; Marino Jeffrey Robert ; O'Sullivan Eugene John ; Sambucetti Carlos Juan ; Schrott Alejandro Gabriel ; Uzoh Cyprian Emeka, Cobalt-tin alloys and their applications for devices, chip interconnections and packaging.
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  4. Koontz Donald E. (Summit NJ) Turner Dennis R. (Chatham Township ; Morris County NJ), Continuous electrochemical processing apparatus.
    상세보기
  5. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
    상세보기
  6. Palnik Karl (Huntingdon Valley PA), Electrolytic plating apparatus.
    상세보기
  7. Dubin Valery, Electroplating apparatus.
    상세보기
  8. Ichinose Hirofumi,JPX ; Sawayama Ippei,JPX ; Hasebe Akio,JPX ; Murakami Tsutomu,JPX ; Hisamatsu Masaya,JPX ; Shinkura Satoshi,JPX ; Ueno Yukie,JPX, Etching method and process for producing a semiconductor element using said etching method.
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  9. Ting Chiu H. ; Holtkamp William H., Integrated vacuum and plating cluster system.
    상세보기
  10. Talieh Homayoun (Santa Clara County CA) Weldon David Edwin (Santa Cruz County CA), Linear polisher and method for semiconductor wafer planarization.
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  11. Lin Mei-Mei (P.O. Box 10160 Taipei TWX), Manufacturing process for making copper-plated aluminum wire and the product thereof.
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  12. Talieh Homoyoun (Sunnyvale CA) Tepman Avi (Cupertino CA) Kieu Hoa Thi (Sunnyvale CA) Wang Chien-Rhone (Milpitas CA), Material deposition method for integrated circuit manufacturing.
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  13. Kadija Igor V. (118 Sherwood Rd. Ridgewood NJ 07450), Method and apparatus for manufacturing interconnects with fine lines and spacing.
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  15. Liu Yauh-Ching ; Perng Dung-Ching, Method of single step damascene process for deposition and global planarization.
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  16. Simon Andrew H. ; Uzoh Cyprian E., Open-bottomed via liner structure and method for fabricating same.
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  17. Ishida Hirofumi (Kanagawa JPX), Plating device for wafer.
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  18. Watts John D. (2 Mohawk Drive Clinton CT 06413), Surface finishing and plating method.
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  19. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA) Nagorski Boguslaw A. (San Jose CA), Wafer polishing machine with fluid bearings.
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