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Interim oxidation of silsesquioxane dielectric for dual damascene process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/476.3
출원번호 US-0311470 (1999-05-13)
발명자 / 주소
  • Cook Robert
  • Greco Stephen E.
  • Hummel John P.
  • Liu Joyce
  • McGahay Vincent J.
  • Mih Rebecca
  • Srivastava Kamalesh
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    McGuireWoods, LLPAbate
인용정보 피인용 횟수 : 2  인용 특허 : 24

초록

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process i

대표청구항

[ Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:] [1.]1. A method of forming a semiconductor device including steps offorming a pattern of resist on a surface of a material,removing a portion of said material in accordance with said pa

이 특허에 인용된 특허 (24)

  1. Cohen Stephan A. (Wappingers Falls NY) McGahay Vincent J. (Poughkeepsie NY) Uttecht Ronald R. (Essex Junction VT), Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits.
  2. Teng Clarence W. (Plano TX), Contact etch process.
  3. Lin Ming-Ren, Damascene process for reduced feature size.
  4. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
  5. Yu Allen S. ; Steffan Paul J. ; Scholer Thomas Charles, Dual damascene process using high selectivity boundary layers.
  6. Avanzino Steven ; Gupta Subhash ; Klein Rich ; Luning Scott D. ; Lin Ming-Ren, Dual damascene with a sacrificial via fill.
  7. Chung Henry Wei-Ming (Cupertino CA), Fabrication of integrated circuits with borderless vias.
  8. Yu Chen-Hua,TWX, Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluor.
  9. Jeng Shin-Puu ; Taylor Kelly J., Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials.
  10. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  11. Wu Kun-Lin,TWX ; Lu Horng-Bor,TWX, Method for preventing poisoned vias and trenches.
  12. Chung Hsien-Ta,TWX ; Yew Tri-Rung,TWX ; Lur Water,TWX, Method of fabricating dual damascene.
  13. Yamaha Takahisa,JPX ; Inoue Yushi,JPX, Method of forming multi-layer wiring utilizing SOG.
  14. Inoue Yushi,JPX ; Yamaha Takahisa,JPX, Method of forming multi-layer wiring utilizing hydrogen silsesquioxane resin.
  15. Nishimura Hiroyuki,JPX ; Adachi Hiroshi,JPX ; Adachi Etsushi,JPX ; Yamamoto Shigeyuki,JPX ; Minami Shintaro,JPX ; Harada Shigeru,JPX ; Tajima Toru,JPX ; Hagi Kimio,JPX, Method of making a semiconductor device.
  16. Yeh Ching-Fa,TWX ; Lee Yueh-Chuan,TWX ; Su Yuh-Ching,TWX ; Wu Kwo-Hau,TWX, Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition.
  17. Liu Jen-Cheng,TWX ; Tsai Chia-Shia,TWX, Method to fabricate self-aligned dual damascene structures.
  18. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  19. Havemann Robert H. (Garland TX) Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX), Porous dielectric material with a passivation layer for electronics applications.
  20. Sun Shi-Chung (Taipei TWX) Chiu Hien-Tien (Taipei TWX) Tsai Ming-Hsing (Chiayi TWX), Process for fabricating tantalum nitride diffusion barrier for copper matallization.
  21. Weiss Keith D. (Midland MI) Frye Cecil L. (Midland MI), Process for forming a coating on a substrate using a silsesquioxane resin.
  22. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  23. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  24. Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.

이 특허를 인용한 특허 (2)

  1. Gronbeck,Dana A.; Gallagher,Michael K.; Calvert,Jeffrey M.; Prokopowicz,Gregory P.; Adams,Timothy G., Electronic device manufacture.
  2. Tomita, Kazuo; Hashimoto, Keiji; Nishioka, Yasutaka; Matsumoto, Susumu; Sekiguchi, Mitsuru; Iwasaki, Akihisa, Method of manufacturing interconnecting structure with vias.
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