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Bonding pads for integrated circuits having copper interconnect metallization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/32
  • H05K-003/34
  • H01L-023/48
  • H01L-029/44
출원번호 US-0346636 (1999-07-01)
발명자 / 주소
  • Shih Wei-Yan
  • Wilson Arthur
  • Subido Willmar
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Honeycutt
인용정보 피인용 횟수 : 45  인용 특허 : 25

초록 ▼

A device having a thin metallic coating, such as tin which forms strong bonds to copper is provided on the bond pads of an integrated circuit having copper metallization; surface oxidation of the coating is self limiting and the oxides are readily removed, further the coated bond pad forms intermeta

대표청구항

[ What is claimed is:] [1.]1. An integrated circuit having copper interconnect metallization which includes an array of bonding pads, said bonding pads consisting essentially of copper and a coating of tin on the copper; and a bond wire attached to at least one of said bonding pads.

이 특허에 인용된 특허 (25)

  1. McMillan ; II Richard Keith (Dearborn MI) Jairazbhoy Vivek Amir (Farmington Hills MI), Anti-skew mounting pads and processing method for electronic surface mount components.
    상세보기
  2. Luc Penelope J. V. (Great Bookham GB2), Bonding and bonded products.
    상세보기
  3. MacKay Colin A. (Austin TX), Bonding electrical leads to pads on electrical components.
    상세보기
  4. Bertolet Allan ; Fiore James ; Gramatski Eberhard, Consolidated chip design for wire bond and flip-chip package technologies.
    상세보기
  5. Tomono Masami (Kokubunji JA) Abe Akira (Takasaki JA) Harada Seiki (Hachioji JA) Sato Kikuji (Kokubunji JA) Takagi Takeshi (Takasaki JA) Kamoshita Genichi (Koganei JA) Oya Yuichiro (Kodaira JA) Saiki , Discrete semiconductor device having polymer resin as insulator and method for making the same.
    상세보기
  6. Carney Francis J. (Gilbert AZ) Carney George F. (Tempe AZ) Mitchell Douglas G. (Tempe AZ), Electrical interconnect and method for forming the same.
    상세보기
  7. Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
    상세보기
  8. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Flip chip interconnections on electronic modules.
    상세보기
  9. Kovac Caroline A. (Ridgefield CT) Noyan Ismail C. (Peekskill NY), High strength low stress encapsulation of interconnected semiconductor devices.
    상세보기
  10. Lau John H., Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips.
    상세보기
  11. Melton Cynthia (Bolingbrook IL) Raleigh Carl (Cary IL) Cholewczynski Kenneth (Streamwood IL) Moore Kevin (Schaumburg IL), Method for forming solder bump interconnections to a solder-plated circuit trace.
    상세보기
  12. Zakel Elke,DEX ; Aschenbrenner Rolf,DEX ; Ostmann Andreas,DEX ; Kasulke Paul,DEX, Method for galvanic forming of bonding pads.
    상세보기
  13. Larson Gary B. (Cheshire CT) Williams Ann S. (Southbury CT) Letize Raymond A. (West Haven CT), Method for manufacture of printed circuit boards.
    상세보기
  14. Rates James T. (Longwood FL), Method for providing known good bare semiconductor die.
    상세보기
  15. Chang Shyh-Ming,TWX ; Ho Shyuan-Jeng,TWX ; Lee Yu-Chi,TWX ; Jeng Jen-Huang,TWX ; Tang Pao-Yun,TWX ; Fang Su-Yu,TWX, Method for tape automated bonding to composite bumps.
    상세보기
  16. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Method of forming interconnections on electronic modules.
    상세보기
  17. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of making contact tip structures.
    상세보기
  18. Gamota Danniel Roman ; Carson George Amos ; Wu Sean Xin ; Bullock Brian J., Microelectronic assembly with collar surrounding integrated circuit component on a substrate.
    상세보기
  19. Hsue Chen-Chiu,TWX ; Chien Sun-Chieh,TWX, Polycide bonding pad structure.
    상세보기
  20. Korsten Gnter (Haan DEX), Procedure for the production of printed circuit boards provided with pads for the insertion of SMDs.
    상세보기
  21. Takahashi Takuya,JPX ; Katsumata Akio,JPX, Semiconductor device and method for manufacturing the same.
    상세보기
  22. Suzuki Kouichi,JPX ; Sato Sadanobu,JPX ; Yamashita Yumiko,JPX, Semiconductor device having metal alloy for electrodes.
    상세보기
  23. Koide Masateru (Kawasaki JPX) Kawamura Yasuo (Kawasaki JPX), Semiconductor device having reformed pad.
    상세보기
  24. Schnepf Dietmar (Esslingen DEX) Reindl Klaus (Pfullingen DEX) Gruner Heiko (Gerlingen DEX) Vogel Friedrich (Reutlingen DEX), Semiconductor electric circuit device with plural-layer aluminum base metallization.
    상세보기
  25. DiGiacomo Giulio (Hopewell Junction NY) Kim Jung-Ihl (Seoul NY KRX) Narayan Chandrasekhar (Hopewell Junction NY) Purushothaman Sampath (Yorktown Heights NY), Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal.
    상세보기

이 특허를 인용한 특허 (45)

  1. Wang, Chung Yu; Lee, Chien-Hsiun, Aluminum cap for reducing scratch and wire-bond bridging of bond pads.
    상세보기
  2. Stuber, Michael A.; Molin, Stuart B., Back-to-back stacked integrated circuit assembly.
    상세보기
  3. Harkins, Brian A., Charge collection side adhesive tape.
    상세보기
  4. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
    상세보기
  5. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
    상세보기
  6. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
    상세보기
  7. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
    상세보기
  8. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
    상세보기
  9. Barth, Hans-Joachim, Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys.
    상세보기
  10. Knuepfer, Bernhard, Die and chip.
    상세보기
  11. Hosseini, Khalil; Kahlmann, Frank; Hoeglauer, Josef; Otremba, Ralf; Meyer-Berg, Georg, Die structure, die arrangement and method of processing a die.
    상세보기
  12. Dinh, Richard Hung Minh; Hooton, Lee E., Dome switch stack and method for making the same.
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  13. Dinh, Richard Hung Minh; Hooton, Lee E., Dome switch stack and method for making the same.
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  14. Dinh, Richard Hung Minh; Hooton, Lee E., Dome switch stack and method for making the same.
    상세보기
  15. Hess, Kevin J.; Lee, Chu-Chung, Localized alloying for improved bond reliability.
    상세보기
  16. Hess, Kevin J.; Lee, Chu-Chung, Localized alloying for improved bond reliability.
    상세보기
  17. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
    상세보기
  18. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.
    상세보기
  19. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
    상세보기
  20. Spencer, Gregory S.; Crabtree, Philip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.
    상세보기
  21. Spencer, Gregory S.; Crabtree, Phillip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.
    상세보기
  22. Li,Yuan, Pad structures to improve board-level reliability of solder-on-pad BGA structures.
    상세보기
  23. Fitzsimmons,John A.; Gambino,Jeffrey P.; Walton,Erick G., Roughened bonding pad and bonding wire surfaces for low pressure wire bonding.
    상세보기
  24. Ellis,Timothy W.; Murdeshwar,Nikhil; Eshelman,Mark A.; Rheault,Christian, Semiconductor copper bond pad surface protection.
    상세보기
  25. Schneegans, Manfred; Leicht, Markus; Woehlert, Stefan; Riedl, Edmund, Semiconductor device.
    상세보기
  26. Minotti, Agatino; Montalto, Gaetano, Semiconductor device with a wire bonding and a sintered region, and manufacturing process thereof.
    상세보기
  27. Agness, John R.; Gu, Mingying, Semiconductor die including a current routing line having non-metallic slots.
    상세보기
  28. Agness, John R.; Gu, Mingying, Semiconductor die including a current routing line having non-metallic slots.
    상세보기
  29. Chang, Hsiao Chuan; Tsai, Tsung Yueh; Lai, Yi Shao; Tong, Ho Ming; Chen, Jian Cheng; Yih, Wei Chi; Hung, Chang Ying; Hsu, Cheng Tsung; Hung, Chih Cheng, Semiconductor package and method for processing and bonding a wire.
    상세보기
  30. Pagani, Alberto; Ziglioli, Federico Giovanni, Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure.
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  31. Nygaard, Paul A.; Molin, Stuart B; Stuber, Michael A; Aubain, Max, Semiconductor-on-insulator with back side heat dissipation.
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  32. Nygaard, Paul A.; Molin, Stuart B.; Stuber, Michael A., Semiconductor-on-insulator with back side strain inducing material.
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  33. Molin, Stuart B.; Nygaard, Paul A.; Stuber, Michael A., Semiconductor-on-insulator with back side support layer.
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  34. Li,Lei; Hortaleza,Edgardo R., Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits.
    상세보기
  35. Deschenes, Michel; Gauvin, Marco; Giguère, Eric, Techniques and structures for testing integrated circuits in flip-chip assemblies.
    상세보기
  36. Wylie,Ian W.; Busta,Heinz H.; Schroeder,David J.; Steckenrider,J. Scott; Wang,Yuchun, Three dimensional integrated circuits.
    상세보기
  37. Bokisa, George S.; Bishop, Craig V.; Kochilla, John R., Tin whisker-free printed circuit board.
    상세보기
  38. Chang, Hsiao Chuan; Tsai, Tsung Yueh; Lai, Yi Shao; Tong, Ho Ming; Chen, Jian Cheng; Yih, Wei Chi; Hung, Chang Ying; Huang, Cheng Wei; Chen, Chih Hsing; Huang, Tai Yuan; Chen, Chieh Ting; Lu, Yi Tsai, Wafer and semiconductor package.
    상세보기
  39. Chittipeddi, Sailesh; Merchant, Sailesh Mansinh, Wire bonding method for copper interconnects in semiconductor devices.
    상세보기
  40. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
    상세보기
  41. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
    상세보기
  42. Gleixner,Robert J.; Danielson,Donald; Paluda,Patrick M.; Naik,Rajan, Wirebond structure and method to connect to a microelectronic die.
    상세보기
  43. Huang, Wen Pin; Hsu, Cheng Tsung; Tseng, Cheng Lan; Hung, Chih Cheng; Chen, Yu Chi, Wirebonded semiconductor package.
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  44. Lee, Ta-Chun, Wirebonded semiconductor package.
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  45. Urashima,Kazuhiro; Ikawa,Tatsuharu; Shiraishi,Mitsuo; Sumi,Hiroshi, Wiring substrate and bonding pad composition.
    상세보기

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