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Communication system and method for different quality of service guarantees for different data flows 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04J-003/16
출원번호 US-0580031 (2000-05-26)
발명자 / 주소
  • Weber Wolf-Dietrich
  • Aras Richard
  • Wingard Drew E.
출원인 / 주소
  • Sonics, Inc.
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 64  인용 특허 : 5

초록 ▼

A system and method for providing service guarantees for data flows between an initiator component and a target component. For each data flow, a set of channels is selected to carry the data flow from initiator to target. The individual performance guarantees of the selected channels are aligned to

대표청구항 ▼

[ What is claimed is:] [1.]1. A method for determining service guarantees for at least one data flow of a plurality of data flows between an initiator component and a target component, said method comprising:mapping a data flow to data channels of components between an initiator component and a targ

이 특허에 인용된 특허 (5)

  1. Lam John ; Huang Frank ; Fuh Eric ; Chen Martin, ATM cell scheduling method and apparatus.
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  2. Keenan Ronald M. ; Barraza Thomas F. ; Caceres Edward R. ; Deptula Joseph A. ; Evans Patrick A. ; Setaro Joseph, Local area network for the transmission and control of audio, video, and computer data.
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  3. McAuley Anthony J. (Glen Ridge NJ), System for the parallel assembly of data transmissions in a broadband network.
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  4. Draney Robert G. ; Lessard Willie, Thrust system for a horizontal directional drill.
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  5. Palmer Douglas A. ; Fellman Ronald D. ; Cruz Rene L., Time-synchronized multi-layer network switch for providing quality of service guarantees in computer networks.
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이 특허를 인용한 특허 (64)

  1. An,Gaeil; Kim,Ki Young; Jang,Jong Soo, Apparatus and method for limiting bandwidths of burst aggregate flows.
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  3. Jayasimha, Doddaballapur N.; Wingard, Drew E.; Hamilton, Stephen W., Apparatus and methods for an interconnect power manager.
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  4. De Lescure, Benoit; Srinivasan, Krishnan, Apparatus and methods for on layer concurrency in an integrated circuit.
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  5. Srinivasan, Krishnan; Khazhakyan, Ruben; Aslanyan, Harutyan; Wingard, Drew E.; Chou, Chien-Chun, Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads.
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  6. Wingard,Drew Eric; Chou,Chien Chun; Masri,Nabil N.; O'Connell,Thomas Wayne; Tomlinson,Jay Scott; Weber,Wolf Dietrich, Communication system and method with configurable posting points.
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  7. Weber,Wolf Dietrich; Aras,Richard; Robinson,Lisa A.; Rosseel,Geert P.; Tomlinson,Jay S.; Wingard,Drew E., Communications system and method with non-blocking shared interface.
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  8. Chou, Chien Chun; Weber, Wolf-Dietrich; Wingard, Drew E., Composing on-chip interconnects with configurable interfaces.
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  9. Weber,Wolf Dietrich; Chou,Chien Chun; Masri,Nabil N.; Meyer,Michael Jude; O'Connell,Thomas Wayne; Synek,Kamil; Tomlinson,Jay Scott; Wingard,Drew Eric, Composing on-chip interconnects with configurable interfaces.
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  10. Guo, Liping; Jayasimha, Doddaballapur N.; Chan, Jeremy, Credit flow control scheme in a router with flexible link widths utilizing minimal storage.
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  11. Klapproth, Peter; Ehmann, Greg; Pfeiffer, Claus, Data-processing system and data-processing method.
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  12. Jayasimha, Doddaballapur N.; Chan, Jeremy; Guo, Liping, Efficient header generation in packetized protocols for flexible system on chip architectures.
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  17. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David, General input/output architecture, protocol and related methods to implement flow control.
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  18. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David, General input/output architecture, protocol and related methods to implement flow control.
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  19. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David, General input/output architecture, protocol and related methods to implement flow control.
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  20. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David M., General input/output architecture, protocol and related methods to implement flow control.
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  21. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David M., General input/output architecture, protocol and related methods to implement flow control.
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  22. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David M., General input/output architecture, protocol and related methods to implement flow control.
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  23. Ajanovic, Jasmin; Harriman, David; Fanning, Blaise; Lee, David M., General input/output architecture, protocol and related methods to implement flow control.
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  24. Ajanovic,Jasmin; Jiang,Hong; Harriman,David, General input/output architecture, protocol and related methods to provide isochronous channels.
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  25. Brinks, Ray; de Lescure, Benoit, Intelligent power controller.
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  26. Brinks, Raymond G.; Lescure, Benoit de; Hamilton, Stephen W., Intelligent power controller.
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  27. Wingard, Drew E.; Chou, Chien-Chun; Hamilton, Stephen W.; Swarbrick, Ian Andrew; Vakilotojar, Vida, Interconnect implementing internal controls.
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  28. Wingard,Drew Eric; Meyer,Michael J.; Rosseel,Geert P.; Robinson,Lisa; Tomlinson,Jay, Logic system with configurable interface.
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  29. Weber, Wolf-Dietrich; Wingard, Drew E.; Hamilton, Stephen W.; Seigneret, Frank, Method and apparatus for a configurable protection architecture for on-chip systems.
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  30. Synek, Kamil; Chou, Chien Chun; Weber, Wolf Dietrich, Method and apparatus for automatic configuration of multiple on-chip interconnects.
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  31. Chou,Chien Chun; Tomlinson,Jay Scott; Weber,Wolf Dietrich; Wingard,Drew Eric; Kasetti,Sricharan, Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems.
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  32. Weber,Wolf Dietrich; Wingard,Drew E., Method and apparatus for configuring an interconnect to implement arbitration.
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  33. Weber,Wolf Dietrich; Chou,Chien Chun; Ebert,Jeffrey Allen; Hamilton,Stephen W.; Meyer,Michael J., Method and apparatus for error handling in networks.
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  34. Weber, Wolf-Dietrich, Method and apparatus for establishing a quality of service model.
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  35. Weber, Wolf-Dietrich; Chou, Chien-Chun; Wingard, Drew E., Method and apparatus for establishing a quality of service model.
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  36. Meyer,Michael Jude; Evans,Scott C.; Synek,Kamil, Method and apparatus for optimizing distributed multiplexed bus interconnects.
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  37. Weber, Wolf-Dietrich, Method and apparatus for scheduling a resource to meet quality-of-service restrictions.
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  38. Weber,Wolf Dietrich, Method and apparatus for scheduling a resource to meet quality-of-service restrictions.
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  39. Weber, Wolf-Dietrich, Method and apparatus for scheduling of requests to dynamic random access memory device.
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  40. Weber,Wolf Dietrich, Method and apparatus for scheduling requests to a resource using a configurable threshold.
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  41. Weber, Wolf-Dietrich, Method and apparatus for scheduling requests using ordered stages of scheduling criteria.
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  43. Tomlinson, Jay S.; Chou, Chien-Chun, Method and apparatus for speculative response arbitration to improve system latency.
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  47. Wingard, Drew E., Methods and apparatus for virtualization in an integrated circuit.
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  48. Chou, Chien-Chun; Kamas, Alan, Methods and apparatuses for time annotated transaction level modeling.
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  51. Ehmann, Gregory; Wingard, Drew E.; Wingen, Neal T., Power manager with a power switch arbitrator.
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  52. Radulescu,Andrei; Goossens,Kees Gerard Willem, Processing system and method for transmitting data.
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  53. Masri,Nabil N.; Weber,Wolf Dietrich; Chou,Chien Chun; Wingard,Drew Eric, Scalable low bandwidth multicast handling in mixed core systems.
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  54. Hamilton, Stephen W., Shared storage for multi-threaded ordered queues in an interconnect.
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  60. Srinivasan, Krishnan; Wingard, Drew E.; Chou, Chien-Chun, Various methods and apparatus for address tiling and channel interleaving throughout the integrated system.
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  61. Wingard, Drew E.; Chou, Chien-Chun; Hamilton, Stephen W.; Swarbrick, Ian Andrew; Vakilotojar, Vida, Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets.
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