초록 ▼

A recognition system comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computers. Each field-programmable logic array device is configured to preprocess data from different respective media inputs and provide f

A recognition system comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computers. Each field-programmable logic array device is configured to preprocess data from different respective media inputs and provide feature extraction vectors to the common vector-input port. Neural networks within the zero-instruction-set computer recognize the input patterns by comparing in parallel their vectors with those stored in each neural network cell. A variety of recognition jobs are made possible by changing the programming on-the-fly of the field-programmable logic array devices to suit each new job.

대표청구항 ▼

[ What is claimed is:] [1.]1. A recognition system, comprising:a dynamically reconfigurable logic device similar to a field programmable gate array and programmed to do a feature extraction process from a media input stream; anda zero instruction set computer (ZISC) device that includes a plurality

[ What is claimed is:] [1.]1. A recognition system, comprising:a dynamically reconfigurable logic device similar to a field programmable gate array and programmed to do a feature extraction process from a media input stream; anda zero instruction set computer (ZISC) device that includes a plurality of neural networks that are connected to simultaneously receive a preprocessed feature extraction data from the dynamically reconfigurable logic device;wherein, a variety of recognition jobs can each be processed by the combination of the logic device and the ZISC by changing said feature extraction process via a dynamic reconfiguration and substantially no hardware changes.