$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method for preparing a conductive pad for electrical connection and conductive pad formed 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-015/00
  • B05D-005/12
출원번호 US-0510996 (2000-02-22)
발명자 / 주소
  • Carlos J. Sambucetti
  • Daniel C. Edelstein
  • John G. Gaudiello
  • Judith M. Rubino
  • George Walker
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Robert M. Trepp
인용정보 피인용 횟수 : 75  인용 특허 : 1

초록

A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal

대표청구항

1. A method for preparing a copper pad surface for electrical connection comprising the steps of:providing a copper pad surface; selectively depositing a protection layer of phosphorus or boron-containing metal alloy on the copper pad surface; and selectively depositing an adhesion layer of a noble

이 특허에 인용된 특허 (1)

  1. Abys Joseph Anthony ; Blair Alan ; Fan Chonglun, Palladium surface coating suitable for wirebonding and process for forming palladium surface coatings.

이 특허를 인용한 특허 (75)

  1. Wirth, Alexandra, Compositions for the currentless deposition of ternary materials for use in the semiconductor industry.
  2. Dubin, Valery M.; Balakrishnan, Sridhar; Bohr, Mark, Designs and methods for conductive bumps.
  3. Dubin, Valery M.; Balakrishnan, Sridhar; Bohr, Mark, Designs and methods for conductive bumps.
  4. Dubin, Valery M.; Balakrishnan, Sridhar; Bohr, Mark, Designs and methods for conductive bumps.
  5. Dubin,Valery M.; Balakrishnan,Sridhar; Bohr,Mark, Designs and methods for conductive bumps.
  6. Nakano, Tetsuo; Maeda, Yukihiro; Asai, Yasutomi; Nagasaka, Takashi, Electrical device having metal pad bonded with metal wiring and manufacturing method thereof.
  7. Chebiam,Ramanan V.; Dubin,Valery M., Electroless plating structure.
  8. Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
  9. Mis, J. Daniel; Engel, Kevin, Electronic devices including metallurgy structures for wire and solder bonding.
  10. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
  11. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods.
  12. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers defining lips.
  13. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
  14. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
  15. Thie, William; Boyd, John M.; Redeker, Fritz C.; Dordi, Yezdi; Parks, John; Arunagiri, Tiruchirapalli; Owczarz, Aleksander; Balisky, Todd; Thomas, Clint; Wylie, Jacob; Schoepp, Alan M., Fluid handling system for wafer electroless plating and associated methods.
  16. Edelstein,Daniel C.; Andricacos,Panayotis C.; Cotte,John M.; Deligianni,Hariklia; Magerlein,John H.; Petrarca,Kevin S.; Stein,Kenneth J.; Volant,Richard P., High Q factor integrated circuit inductor.
  17. Estepa, Erwin R.; Medina, Joel T.; Azurin, Maria Alesssandra; Ano, Kazuaki, Low cost substrate for an integrated circuit device with bondpads free of plated gold.
  18. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
  19. Izumi, Yoshihiro; Chikama, Yoshimasa; Kawashima, Satoshi; Hashimoto, Takaharu, Metal line, method for fabricating the metal line, thin film transistor employing the metal line and display device.
  20. Thie, William; Boyd, John M.; Redeker, Fritz C.; Dordi, Yezdi; Parks, John; Arunagiri, Tiruchirapalli; Owczarz, Aleksander; Balisky, Todd; Thomas, Clint; Wylie, Jacob; Schoepp, Alan M., Method and apparatus for wafer electroless plating.
  21. Farnworth, Warren M., Method for fabricating semiconductor components with conductors having wire bondable metalization layers.
  22. Edelstein, Daniel C.; Andricacos, Panayotis C.; Cotte, John M.; Deligianni, Hariklia; Magerlein, John H.; Petrarca, Kevin S.; Stein, Kenneth J.; Volant, Richard P., Method of fabricating a high Q factor integrated circuit inductor.
  23. Edelstein, Daniel C.; Andricacos, Panayotis C.; Cotte, John M.; Deligianni, Hariklia; Magerlein, John H.; Petrarca, Kevin S.; Stein, Kenneth J.; Volant, Richard P., Method of fabricating a high Q factor integrated circuit inductor.
  24. Edelstein, Daniel C.; Kang, Sung Kwon; McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Walker, George F., Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped.
  25. Edelstein,Daniel C.; Kang,Sung Kwon; McGlashan Powell,Maurice; O'Sullivan,Eugene J.; Walker,George F., Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped.
  26. Mao, Jianhong; Han, Fengqin; Wang, Zhiwei; Chang, Wenfen, Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package.
  27. Rinne,Glenn A.; Mis,J. Daniel, Methods of forming bumps using barrier layers as etch masks.
  28. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
  29. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
  30. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
  31. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
  32. Mis, J. Daniel; Engel, Kevin, Methods of forming metallurgy structures for wire and solder bonding.
  33. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
  34. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
  35. Fang, Jen-Kuang, Multi-chip module packaging device using flip-chip bonding technology.
  36. Gleason,Jeffery N.; Lindgren,Joseph T., Nickel bonding cap over copper metalized bondpads.
  37. Gleason,Jeffery N.; Lindgren,Joseph T., Nickel bonding cap over copper metalized bondpads.
  38. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
  39. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
  40. Bauer, Michael; Haimerl, Alfred; Kessler, Angela; Mahler, Joachim; Schober, Wolfgang, Semiconductor chip comprising a metal coating structure and associated production method.
  41. Farnworth, Warren M., Semiconductor component having conductors with wire bondable metalization layers.
  42. Farnworth,Warren M., Semiconductor component having conductors with wire bondable metalization layers.
  43. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  44. Beer, Gottfried; Foerg, Raimund; Hoegerl, Juergen, Semiconductor device having solderable and bondable electrical contact pads.
  45. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
  46. Heng, Mung Suan; Tan, Kok Chua; Leong, Vince Chan Seng; Johnson, Mark S., Stacked microfeature devices and associated methods.
  47. Sidhu, Rajen S.; Dani, Ashay A.; Renavikar, Mukul P., Substrate metallization and ball attach metallurgy with a novel dopant element.
  48. Lee, Young Woo; Lee, Im Bok; Hong, Sung Jae; Moon, Jeong Tak, Tin-based solder ball and semiconductor package including the same.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  60. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  61. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  62. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  63. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Ueno, Kazuyoshi; Osaka, Tetsuya; Takano, Nao, ULSI wiring and method of manufacturing the same.
  70. Sebesta, Robert David; Wilson, James Warren, Variable thickness pads on a substrate surface.
  71. Uhlig, Albrecht; Gaida, Josef; Suchentrunk, Christof, Wire bondable surface for microelectronic devices.
  72. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
  73. Gleixner, Robert J.; Danielson, Donald; Paluda, Patrick M.; Naik, Rajan, Wirebond structure and method to connect to a microelectronic die.
  74. Gleixner,Robert J.; Danielson,Donald; Paluda,Patrick M.; Naik,Rajan, Wirebond structure and method to connect to a microelectronic die.
  75. Kazuhisa Sato JP; Hiroyuki Hashimoto JP, Wired board and method of producing the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로